On Mon, Oct 27, 2025 at 04:59:24PM +0200, Abel Vesa wrote: > Describe the Universal Bandwidth Compression (UBWC) configuration > for the new Glymur platform. > > Reviewed-by: Dmitry Baryshkov <[email protected]> > Signed-off-by: Abel Vesa <[email protected]> > --- > drivers/soc/qcom/ubwc_config.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c > index > 15d373bff231d770e00fe0aee1b5a95c7b8a6305..7cca2afb68e3e9d33f3066f1deb3b9fcc01641a1 > 100644 > --- a/drivers/soc/qcom/ubwc_config.c > +++ b/drivers/soc/qcom/ubwc_config.c > @@ -218,11 +218,23 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = { > .macrotile_mode = true, > }; > > +static const struct qcom_ubwc_cfg_data glymur_data = { > + .ubwc_enc_version = UBWC_5_0, > + .ubwc_dec_version = UBWC_5_0, > + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | > + UBWC_SWIZZLE_ENABLE_LVL3, > + .ubwc_bank_spread = true, > + /* TODO: highest_bank_bit = 15 for LP_DDR4 */ > + .highest_bank_bit = 16,
As I started reviewing UBWC bits and pieces... Could you please check, according to the document I'm looking at this configuration is not correct. > + .macrotile_mode = true, > +}; > + -- With best wishes Dmitry
