Since DPU 8.0 there is a separate register for the second rectangle,
which needs to be programmed with the UBWC config if multirect is being
used. Write pipe's UBWC configuration to the correct register.
Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index b66c4cb5760c..a99e33230514 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -72,6 +72,7 @@
#define SSPP_EXCL_REC_XY_REC1 0x188
#define SSPP_EXCL_REC_SIZE 0x1B4
#define SSPP_EXCL_REC_XY 0x1B8
+#define SSPP_UBWC_STATIC_CTRL_REC1 0x1c0
#define SSPP_CLK_CTRL 0x330
/* SSPP_SRC_OP_MODE & OP_MODE_REC1 */
@@ -215,7 +216,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe
*pipe,
u32 chroma_samp, unpack, src_format;
u32 opmode = 0;
u32 fast_clear = 0;
- u32 op_mode_off, unpack_pat_off, format_off;
+ u32 op_mode_off, unpack_pat_off, format_off, ubwc_static_ctrl_off;
if (!ctx || !fmt)
return;
@@ -225,10 +226,17 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe
*pipe,
op_mode_off = SSPP_SRC_OP_MODE;
unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
format_off = SSPP_SRC_FORMAT;
+ ubwc_static_ctrl_off = SSPP_UBWC_STATIC_CTRL;
} else {
op_mode_off = SSPP_SRC_OP_MODE_REC1;
unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
format_off = SSPP_SRC_FORMAT_REC1;
+
+ /* reg wasn't present before DPU 8.0 */
+ if (ctx->mdss_ver->core_major_ver >= 8)
+ ubwc_static_ctrl_off = SSPP_UBWC_STATIC_CTRL_REC1;
+ else
+ ubwc_static_ctrl_off = SSPP_UBWC_STATIC_CTRL;
}
c = &ctx->hw;
@@ -281,24 +289,24 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe
*pipe,
switch (ctx->ubwc->ubwc_enc_version) {
case UBWC_1_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_static_ctrl_off,
fast_clear | (ctx->ubwc->ubwc_swizzle &
0x1) |
BIT(8) |
(hbb << 4));
break;
case UBWC_2_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_static_ctrl_off,
fast_clear | (ctx->ubwc->ubwc_swizzle) |
(hbb << 4));
break;
case UBWC_3_0:
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_static_ctrl_off,
BIT(30) | (ctx->ubwc->ubwc_swizzle) |
(hbb << 4));
break;
case UBWC_4_0:
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_REG_WRITE(c, ubwc_static_ctrl_off,
MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
break;
}
--
2.47.3
