Commit a36c533ad3e1 ("drm/bridge: samsung-dsim: Always flush display
FIFO on vsync pulse") intends to enable FIFO flushing at v-sync pulse by
not setting the active-low MFLUSH_VS bit.However, in Exynos 7870 DSIM, the MFLUSH_VS bit is active-high. There is no publicly available documentation to the best of my knowledge, but downstream kernel code [1] supports this claim. Enable the bit for Exynos 7870. Cc: [email protected] # v6.17 and later Link: https://github.com/samsungexynos7870/android_kernel_samsung_exynos7870/blob/a3762bb1761aec8543fae511b087da620e24cee5/drivers/video/fbdev/exynos/decon_7870/dsim_reg_7870.c#L699 [1] Signed-off-by: Kaustabh Chakraborty <[email protected]> --- drivers/gpu/drm/bridge/samsung-dsim.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 975f8b50ae660..91f230953a49f 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1089,6 +1089,13 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi) reg |= DSIM_HBP_DISABLE_MODE; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) reg |= DSIM_HSA_DISABLE_MODE; + + /* + * For some hardware types, DSIM_MFLUSH_VS bit needs to be + * enabled explicitly. + */ + if (dsi->plat_data->hw_type == DSIM_TYPE_EXYNOS7870) + reg |= DSIM_MFLUSH_VS; } if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) -- 2.52.0
