On Mon, 9 Feb 2026 15:22:09 +0000 Liviu Dudau <[email protected]> wrote:
> > > Ultimately the role of this RFC is to start a discussion and to figure > > > out a path > > > forward for CSF GPUs where we want now to tighen a bit the formats we > > > support and > > > add PBHA and in the future we want to add support for v15+ page formats. > > > > PBHA is definitely an area for discussion. AIUI there are out-of-tree > > patches floating about for CPU support, but it hasn't been upstreamed. I > > don't know if any serious attempt has been made to push it upstream, but > > it's tricky because the architecture basically just says "IMPLEMENTATION > > DEFINED" which means you are no longer coding to the architecture but a > > specific implementation - and there's remarkably little documentation > > about what PBHA is used for in practice. > > > > I haven't looked into the GPU situation with PBHA - again it would be > > good to have more details on how the bits would be set. > > I have a patch series that adds support in Panthor to apply some PBHA bits > defined > in the DT based on an ID also defined in the DT and passed along as a VM_BIND > parameter > if you want to play with it. However I have no direct knowledge on which PBHA > values > would make a difference on the supported platforms (RK3xxx for example). I don't know if that's what it's going be used for, but one very specific use case I'd like to see this PBHA extension backed by is "read-zero/write-discard" behavior that's needed for sparse bindings. Unfortunately, I've not heard on any HW-support for that in older gens...
