The NPU 60XX uses the default boot params location specified
in the firmware image header, consistent with earlier generations.
Remove the unnecessary MMIO register write, freeing the AON register
for future use.
Fixes: 44e4c88951fa ("accel/ivpu: Implement warm boot flow for NPU6 and unify
boot handling")
Signed-off-by: Andrzej Kacprowski <[email protected]>
---
drivers/accel/ivpu/ivpu_hw_40xx_reg.h | 6 ------
drivers/accel/ivpu/ivpu_hw_ip.c | 1 -
2 files changed, 7 deletions(-)
diff --git a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
index 421242acb184..fc0ee8d637f9 100644
--- a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
+++ b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
@@ -121,12 +121,6 @@
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY
0x0003006cu
#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK
GENMASK(7, 0)
-#define VPU_40XX_HOST_SS_AON_RETENTION0
0x0003000cu
-#define VPU_40XX_HOST_SS_AON_RETENTION1
0x00030010u
-#define VPU_40XX_HOST_SS_AON_RETENTION2
0x00030014u
-#define VPU_40XX_HOST_SS_AON_RETENTION3
0x00030018u
-#define VPU_40XX_HOST_SS_AON_RETENTION4
0x0003001cu
-
#define VPU_40XX_HOST_SS_AON_IDLE_GEN
0x00030200u
#define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK
BIT_MASK(0)
#define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK
BIT_MASK(1)
diff --git a/drivers/accel/ivpu/ivpu_hw_ip.c b/drivers/accel/ivpu/ivpu_hw_ip.c
index 959984c54341..37f95a0551ed 100644
--- a/drivers/accel/ivpu/ivpu_hw_ip.c
+++ b/drivers/accel/ivpu/ivpu_hw_ip.c
@@ -931,7 +931,6 @@ static int soc_cpu_boot_40xx(struct ivpu_device *vdev)
static int soc_cpu_boot_60xx(struct ivpu_device *vdev)
{
- REGV_WR64(VPU_40XX_HOST_SS_AON_RETENTION1, vdev->fw->mem_bp->vpu_addr);
soc_cpu_set_entry_point_40xx(vdev, vdev->fw->cold_boot_entry_point);
return 0;
--
2.34.1
