From: Hugo Villeneuve <[email protected]> Add proper support for the optional Wifi and Bluetooth configuration on VAR-SOM-6UL so that it works out of the box, without any custom scripts. The Wifi/BT module support is mutually exclusive with SD card interface.
Signed-off-by: Hugo Villeneuve <[email protected]> --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 18 ++--- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 18 +++++ .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi | 75 +++++++++++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 15 ++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 18 +++++ .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++++ 7 files changed, 151 insertions(+), 10 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 4f212569d2cdd..b81668dcaccf4 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ul-var-som-concerto.dtb \ + imx6ul-var-som-concerto-full.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-aster.dtb \ imx6ull-colibri-emmc-aster.dtb \ @@ -378,6 +379,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ull-uti260b.dtb \ imx6ull-var-som-concerto.dtb \ + imx6ull-var-som-concerto-full.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index dd4ecff1eb786..af8c5d2db53d4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -19,6 +19,14 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_gpio_dvfs: reg-gpio-dvfs { compatible = "regulator-gpio"; regulator-min-microvolt = <1300000>; @@ -68,9 +76,6 @@ ethphy0: ethernet-phy@1 { }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 @@ -97,13 +102,6 @@ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 >; }; - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts new file mode 100644 index 0000000000000..519250b31db24 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6UL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ul-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; + compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi new file mode 100644 index 0000000000000..6d16ff7909dab --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + reg_sd1_vmmc: regulator_sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VMMC1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_wifi>; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_32k_clk: 32kclkgrp { + /* + * For TP option, an additional oscillator is assembled on the + * SOM to provide 32 kHz to the WiFi module. Without TP option, + * this pin is configured to provide the 32 KHz clock to the + * WiFi module. + */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 + >; + }; +}; + +&tsc { + status = "disabled"; +}; + +/* Bluetooth UART */ +&uart2 { + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_bt>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */ + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 35a0c0b3603fd..b4e6a9316dd81 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -15,3 +15,18 @@ / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts new file mode 100644 index 0000000000000..7c0e313603630 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi index ba482a97623b2..3067ff6a1bc74 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -13,3 +13,18 @@ / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ull", "fsl,imx6ull"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; -- 2.47.3
