Hi Krzysztof,
On 3/20/2026 5:19 PM, Krzysztof Kozlowski wrote:
On Thu, Mar 19, 2026 at 06:40:23PM +0800, Damon Ding wrote:
The RK3588 eDP controller needs the video datapath clock "hclk" to work
well. Previously, it works without explicitly adding this clock because
the 'rockchip,vo-grf = <&vo1_grf>' property implicitly enables HCLK_VO1.
Fixes: f855146263b1 ("dt-bindings: display: rockchip: analogix-dp: Add support for
RK3588")
Signed-off-by: Damon Ding <[email protected]>
---
.../bindings/display/rockchip/rockchip,analogix-dp.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
index d99b23b88cc5..d2bc8636b626 100644
---
a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
+++
b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
@@ -26,7 +26,9 @@ properties:
items:
- const: dp
- const: pclk
- - const: grf
+ - enum:
+ - grf
+ - hclk
You just told me it is the same clock, no? I asked that and you
confirmed? Or you replied with an answer not relevant to the question?
Aha, I may have misunderstood your earlier advice as meaning that since
the RK3576 and RK3588 platforms share the same design, their clock
dependencies should also be identical.
The 'grf' clock and 'hclk' clock are different.
On RK3399, the GRF clock is for accessing VIO GRF registers.
On RK3588/RK3576, the eDP 'hclk' is required as it is the parent clock
of 'pclk' in the AHB bus topology.
If this device takes reference to grf, why does it also take grf clock?
Devices MUST NOT take clocks on behalf of other devices, so please
answer with a list of all clock inputs according to datasheet/manual.
On earlier platforms, the GRF was not partitioned into separate
functional small GRF units as on newer designs. Therefore, the 'grf'
clock was designed as the clock dependency for all relevant modules.
For RK3588/RK3576 eDP module, the list of all clock inputs is:
CLK_EDP0_24M: Reference clock.
PCLK_EDP0: AHB clock.
HCLK_VO1/HCLK_VO0_ROOT: Video datapath clock.
It would be better to add above comments as the descriptions of these
clocks in yaml.
Best regards,
Damon
