CP_ALWAYS_ON_COUNTER is not save-restored during preemption, so it won't
provide accurate data about the 'submit' when preemption is enabled.
Switch to CP_ALWAYS_ON_CONTEXT which is preemption safe.
Fixes: e7ae83da4a28 ("drm/msm/a6xx: Implement preemption for a7xx targets")
Signed-off-by: Akhil P Oommen <[email protected]>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 50bd7aa4e792..f8cb8b578661 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -347,7 +347,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
* GPU registers so we need to add 0x1a800 to the register value on A630
* to get the right value from PM4.
*/
- get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
+ get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT,
rbmemptr_stats(ring, index, alwayson_start));
/* Invalidate CCU depth and color */
@@ -388,7 +388,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
rbmemptr_stats(ring, index, cpcycles_end));
- get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
+ get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT,
rbmemptr_stats(ring, index, alwayson_end));
/* Write the fence to the scratch register */
@@ -457,7 +457,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct msm_ringbuffer *ring = submit->ring;
- u32 rbbm_perfctr_cp0, cp_always_on_counter;
+ u32 rbbm_perfctr_cp0, cp_always_on_context;
unsigned int i, ibs = 0;
adreno_check_and_reenable_stall(adreno_gpu);
@@ -480,14 +480,14 @@ static void a7xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
if (adreno_is_a8xx(adreno_gpu)) {
rbbm_perfctr_cp0 = REG_A8XX_RBBM_PERFCTR_CP(0);
- cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_COUNTER;
+ cp_always_on_context = REG_A8XX_CP_ALWAYS_ON_CONTEXT;
} else {
rbbm_perfctr_cp0 = REG_A7XX_RBBM_PERFCTR_CP(0);
- cp_always_on_counter = REG_A6XX_CP_ALWAYS_ON_COUNTER;
+ cp_always_on_context = REG_A6XX_CP_ALWAYS_ON_CONTEXT;
}
get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index,
cpcycles_start));
- get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring,
index, alwayson_start));
+ get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring,
index, alwayson_start));
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
OUT_RING(ring, CP_SET_THREAD_BOTH);
@@ -535,7 +535,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
}
get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index,
cpcycles_end));
- get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring,
index, alwayson_end));
+ get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring,
index, alwayson_end));
/* Write the fence to the scratch register */
if (adreno_is_a8xx(adreno_gpu)) {
--
2.51.0
