On Fri, 09 Jan 2026 16:38:06 +0800, yuanjie yang wrote:
> During DPU runtime suspend, calling dev_pm_opp_set_rate(dev, 0) drops
> the MMCX rail to MIN_SVS while the core clock frequency remains at its
> original (highest) rate. When runtime resume re-enables the clock, this
> may result in a mismatch between the rail voltage and the clock rate.
Applied to msm-next, thanks!
[1/2] drm/msm/dpu: fix mismatch between power and frequency
https://gitlab.freedesktop.org/lumag/msm/-/commit/bc1dccc518cc
Best regards,
--
With best wishes
Dmitry
