Few targets have lesser SSPP line width compared to mixer width, SSPP line width also needs to be considered during mode valid to avoid failures during atomic_check.
Signed-off-by: Vishnu Saini <[email protected]> --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 6bf7c46379ae..af245c44959d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1591,6 +1591,7 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc, { struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); u64 adjusted_mode_clk; + u32 max_width; /* if there is no 3d_mux block we cannot merge LMs so we cannot * split the large layer into 2 LMs, filter out such modes @@ -1613,11 +1614,14 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc, return MODE_CLOCK_HIGH; /* - * max crtc width is equal to the max mixer width * 2 and max height is 4K + * max crtc width is equal to the min of max mixer width * 2 and max sspp line width * 2 + * max height is 4K */ - return drm_mode_validate_size(mode, - 2 * dpu_kms->catalog->caps->max_mixer_width, - 4096); + max_width = 2 * min_t(u32, + dpu_kms->catalog->caps->max_mixer_width, + dpu_kms->catalog->caps->max_linewidth); + + return drm_mode_validate_size(mode, max_width, 4096); } /** --- base-commit: 6efced27f5df9d7a57e4847fe2898cdd19f72311 change-id: 20260328-msm-next-70eb896ff64d Best regards, -- Vishnu Saini <[email protected]>
