On 4/1/26 4:17 AM, Alexander Koskovich wrote: > A8XX GPUs have two sets of protect registers: 64 global slots and 16 > pipe specific slots. The last-span-unbound feature is only available > on pipe protect registers, and should always target pipe slot 15. > > This matches the downstream driver which hardcodes pipe slot 15 for > all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on > A810. > > Signed-off-by: Alexander Koskovich <[email protected]> > --- > drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index 5af82d43f1e4..63387ee9b04a 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -252,11 +252,12 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) > } > > /* > - * Last span feature is only supported on PIPE specific register. > - * So update those here > + * Last span setting is only being applied to the last pipe specific > + * register. Hence duplicate the last span from protect reg into the > + * BR and BV protect reg pipe 15. > */ > - a8xx_write_pipe(gpu, PIPE_BR, > REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); > - a8xx_write_pipe(gpu, PIPE_BV, > REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); > + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); > + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
I think this is a better fix than: https://lore.kernel.org/linux-arm-msm/[email protected]/ which will let us bring back the BUILD_BUG_ON.. WDYT Akhil? FWIW KGSL just hardcodes the number 15 here as well.. may make it configurable if that ever changes Reviewed-by: Konrad Dybcio <[email protected]> Konrad
