On Mon, 13 Jul 2026 12:38:03 +0200, AngeloGioacchino Del Regno wrote:
> Changes in v3:
> - Actually sent the correct patch series (sorry, I had messed up v2)
> - Added definitions for minimum and maximum PLL rates
>
> Changes in v2:
> - Added a few comments and fix scheduling while atomic issue in clk
> enable ops by waiting with udelay() instead
> - Removed one unnecessary delay after clk/pwr isolation disablement
>
> [...]
Applied, thanks!
[1/2] dt-bindings: phy: mediatek,dsi-phy: Add support for MT8196
commit: 215cd5def8eca1c2aa7ca043483d96155a1c3ed6
[2/2] phy: mediatek: Add support for MT8196 MIPI DSI PHY
commit: 2ec9c210c1f931389709aee403d28e4f32676385
Best regards,
--
~Vinod
