Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Pre-Volta primary planes (base507c, base827c, base907c) expose alpha formats but are missing `.blend_modes` assignments, leaving the DRM core warning unfixed for these architectures. --
--- Patch [1]: [PATCH v2 1/3] drm/nouveau/kms/nv50-: Add .blend_modes to nv50_wndw_func --- commit 742edbbf0331352f33ff9e6b7929be21b191145a Author: Lyude Paul <[email protected]> Subject: drm/nouveau/kms/nv50-: Add .blend_modes to nv50_wndw_func At the moment, we currently (incorrectly) only expose a blend property on the plane if we have a nv50_wndw_func->blend_set function for the given wndw type. But we need to expose a blend property for all types of planes that can display color formats with an alpha channel. Prepare for doing this by introducing a way of looking up the supported blend modes for a type of wndw by introducing .blend_modes, which describes all possible blending modes nouveau currently supports for a type of wndw. > diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h > b/drivers/gpu/drm/nouveau/dispnv50/wndw.h > index 90d100514bef2..81af5c3369d4c 100644 > --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h > +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h [ ... ] > @@ -74,6 +76,7 @@ struct nv50_wndw_func { > int (*image_clr)(struct nv50_wndw *); > int (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); > int (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); > + unsigned int blend_modes; [Severity: Medium] Does this patch miss setting .blend_modes for pre-Volta primary planes? Looking at base507c, base827c, and base907c in the driver, they expose alpha formats but don't seem to have .blend_modes assignments added in this patch. For example, in drivers/gpu/drm/nouveau/dispnv50/base507c.c: static const struct nv50_wndw_func base507c = { .acquire = base507c_acquire, .release = base507c_release, ... .image_clr = base507c_image_clr, .update = base507c_update, }; Without setting .blend_modes for these architectures, will they still trigger the DRM core warning "[PLANE:%d:%s] pixel format with alpha exposed but blend mode not setup" during display initialization on Tesla through Pascal hardware? > > int (*update)(struct nv50_wndw *, u32 *interlock); > }; -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=1
