On Wed, Aug 26, 2026 at 07:15:43PM +0530, Vinayak Katoch wrote: > Add an optional memory-region property to the context bank node schema. > The driver uses its presence to identify a context bank as dedicated for > extended IOVA mapping and programs the SMMU with an iommu-addresses > range to push allocations into the wider address space.
I hope you are not solving in a third or fourth way the same problem that Iris/Venus, QDA and one more block have. > > Relax #address-cells to enum: [1, 2] and #size-cells to enum: [0, 2] to > allow platforms that require 64-bit values in iommu-addresses to pass > binding validation. > > Signed-off-by: Vinayak Katoch <[email protected]> > --- > Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml > b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml > index e945c8ba75e3..f9830ef37814 100644 > --- a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml > +++ b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml > @@ -73,10 +73,10 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint32-array > > "#address-cells": > - const: 1 > + enum: [1, 2] > > "#size-cells": > - const: 0 > + enum: [0, 2] > > patternProperties: > "(compute-)?cb@[0-9]*$": > @@ -98,6 +98,14 @@ patternProperties: > minItems: 1 > maxItems: 10 > > + memory-region: > + maxItems: 1 > + description: > + Phandle to a reserved-memory node whose iommu-addresses property > + blocks the lower IOVA range, forcing allocations into the extended > + address space. Its presence marks this context bank as an extended > + mapping bank. So far looks the same as: https://lore.kernel.org/all/[email protected]/ If it is not the same problem, then please explain. Otherwise wait for resolution of Iris patchset. Best regards, Krzysztof
