On Fri, 11 Sep 2026 09:40:13 +0200, AngeloGioacchino Del Regno wrote:
> Changes in v2:
> - Fixed commit description of patch [2/2] (Mani)
>
> This series adds two fixes for the MT8195-class HDMI PHY, found in
> MT8195, MT8188 and Genio variants.
>
> This is fixing PLL calculation, and TMDS clock dividers, to achieve
> all of the modes requiring data rates higher than 3.4Gbps, with the
> successfully tested target being 3840x2160@60Hz.
>
> [...]
Applied, thanks!
[1/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow
commit: de7f29a1fe1dc2864d8a47f8c39d508442cae167
[2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting
commit: 486a70ef848264dcf9a57f0bb0452848db9537de
Best regards,
--
~Vinod
