On Mon, 14 Sep 2026 09:33:28 +0800, Chaoyi Chen wrote:
> This series is dedicated to enhancing the DSI controller and PHY timing
> interaction, refining the lane rate calculation, and addressing the
> associated hardware limitations.
>
> Changes in v5:
> - Link to v4:
> https://lore.kernel.org/all/[email protected]/
> - Change the upper bound check for target_mbps from < to <= (sashiko).
>
> [...]
Applied, thanks!
[1/3] drm/rockchip: dsi: Add maximum per lane bit rate calculation
commit: 3c58af05953af5ab120e2c9061d7bdedde0d1bfd
[2/3] drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types
commit: 5363e01e4ff03a204cab85292b89cf90c2d1b101
Best regards,
--
Heiko Stuebner <[email protected]>
