On Wed, Oct 26, 2011 at 11:41 AM, <j.glisse at gmail.com> wrote:
> From: Jerome Glisse <jglisse at redhat.com>
>
> Cayman seems to be particularly sensitive to read cache returning
> old data after bind/unbind to GTT. Flush read cache for GTT range
> with each fences for all new hw. Should fix several rendering glitches.
> Like
>
> V2 flush whole address space
> V3 also flush shader read cache
>
> https://bugs.freedesktop.org/show_bug.cgi?id=40221
> https://bugs.freedesktop.org/show_bug.cgi?id=38022
> https://bugzilla.redhat.com/show_bug.cgi?id=738790
>
> Signed-off-by: Jerome Glisse <jglisse at redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> ?drivers/gpu/drm/radeon/evergreen_blit_kms.c | ? ?4 ++--
> ?drivers/gpu/drm/radeon/r600.c ? ? ? ? ? ? ? | ? 16 ++++++++++++++++
> ?drivers/gpu/drm/radeon/r600_blit_kms.c ? ? ?| ? ?4 ++--
> ?3 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
> b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
> index dcf11bb..e9aeeed 100644
> --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
> +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
> @@ -613,9 +613,9 @@ int evergreen_blit_init(struct radeon_device *rdev)
> ? ? ? ?rdev->r600_blit.primitives.set_default_state = set_default_state;
>
> ? ? ? ?rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
> - ? ? ? rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
> + ? ? ? rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
> ? ? ? ?rdev->r600_blit.ring_size_common += 5; /* done copy */
> - ? ? ? rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
> + ? ? ? rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
>
> ? ? ? ?rdev->r600_blit.ring_size_per_loop = 74;
>
> diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
> index 12470b0..1f007ad 100644
> --- a/drivers/gpu/drm/radeon/r600.c
> +++ b/drivers/gpu/drm/radeon/r600.c
> @@ -2331,6 +2331,14 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
> ? ? ? ?if (rdev->wb.use_event) {
> ? ? ? ? ? ? ? ?u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
> ? ? ? ? ? ? ? ? ? ? ? ?(u64)(rdev->fence_drv.scratch_reg -
> rdev->scratch.reg_base);
> + ? ? ? ? ? ? ? /* flush read cache over gart */
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? PACKET3_VC_ACTION_ENA |
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? PACKET3_SH_ACTION_ENA);
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, 0xFFFFFFFF);
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, 0);
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, 10); /* poll interval */
> ? ? ? ? ? ? ? ?/* EVENT_WRITE_EOP - flush caches, send int */
> ? ? ? ? ? ? ? ?radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
> ? ? ? ? ? ? ? ?radeon_ring_write(rdev,
> EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
> @@ -2339,6 +2347,14 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
> ? ? ? ? ? ? ? ?radeon_ring_write(rdev, fence->seq);
> ? ? ? ? ? ? ? ?radeon_ring_write(rdev, 0);
> ? ? ? ?} else {
> + ? ? ? ? ? ? ? /* flush read cache over gart */
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? PACKET3_VC_ACTION_ENA |
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? PACKET3_SH_ACTION_ENA);
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, 0xFFFFFFFF);
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, 0);
> + ? ? ? ? ? ? ? radeon_ring_write(rdev, 10); /* poll interval */
> ? ? ? ? ? ? ? ?radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
> ? ? ? ? ? ? ? ?radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT)
> | EVENT_INDEX(0));
> ? ? ? ? ? ? ? ?/* wait for 3D idle clean */
> diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c
> b/drivers/gpu/drm/radeon/r600_blit_kms.c
> index c4cf130..36e62f2 100644
> --- a/drivers/gpu/drm/radeon/r600_blit_kms.c
> +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
> @@ -500,9 +500,9 @@ int r600_blit_init(struct radeon_device *rdev)
> ? ? ? ?rdev->r600_blit.primitives.set_default_state = set_default_state;
>
> ? ? ? ?rdev->r600_blit.ring_size_common = 40; /* shaders + def state */
> - ? ? ? rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
> + ? ? ? rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
> ? ? ? ?rdev->r600_blit.ring_size_common += 5; /* done copy */
> - ? ? ? rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
> + ? ? ? rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
>
> ? ? ? ?rdev->r600_blit.ring_size_per_loop = 76;
> ? ? ? ?/* set_render_target emits 2 extra dwords on rv6xx */
> --
> 1.7.1
>
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