Hi,
This series converts QAIC_(PARTIAL_)EXECUTE_BO to use the DRM Scheduler.
The immediate user-visible change is that BOs can use DMA-BUF resv
objects to track their use. Completion fences are attached to the BOs
sent with an EXEC ioctl, allowing userspace to synchronize through
DMA-BUF polling/epoll rather than relying on WAIT_BO.
The scheduler's credit system is used to prevent oversubmission. This
removes the requirement that every request generated by a BO fit within
the device's FIFO at the time it is submitted. BOs with large request
lists, including those resulting from fragmented memory, are split into
multiple jobs and submitted as space becomes available.
Implementation Notes:
Each DBC has its own scheduler and one scheduler entity, rather than
creating a entity per execute command or BO. This is to keep as close to
the current submission ordering.
When splitting BOs into multiple jobs, a dependency fence is added to
each subsequent job. This prevents the final request, which contains the
relevant semaphore and doorbell commands, from being submitted before the
rest of the BO is sent.
Each job is assigned credits in proportion to the number of DBC request
entries it submits. Since the requested size of the submission buffer
is not known until DBC activation, and the DBCs are initialized during
driver initialization, each scheduler is created with a fixed 64K
credit. At DBC activation, a per-DBC scaling ratio is calculated from
the FIFO size. The ratio is rounted up when necessary, which can lead to
small amounts of the FIFO being unused.
The final patch uses this and the DRM Scheduler's credit limit to support
buffers smaller than those requested by the user (preventing failures
occuring due to limited DMA-coherent memory).
Each scheduler is given a WQ_PERCPU submission workqueue with one active
worker. The default ordered workqueue showed a throughput regression
when large (32+) numbers of devices submitted large (1K+) numbers of
jobs since the single workqueue provided could not dispatch fast enough.
Testing:
- Ran checkpatch.pl
- Built and performed functional testing against v7.3-rc3
- Production use with kernels v6.8 through v7.0 with 96+ devices and
16k+ in-flight jobs.
Target tree: drm-misc-next
Carl Vanderlip (6):
accel/qaic: Centralize execution info
accel/qaic: Replace transfer completion with dma-fence
accel/qaic: Isolate hw submission
accel/qaic: Use DRM_SCHED to handle FIFO submission
accel/qaic: Split oversized BO requests into multiple jobs
accel/qaic: Use reduced size allocation for FIFOs
drivers/accel/qaic/Kconfig | 1 +
drivers/accel/qaic/Makefile | 2 +
drivers/accel/qaic/qaic.h | 182 +++++++-
drivers/accel/qaic/qaic_control.c | 36 +-
drivers/accel/qaic/qaic_data.c | 710 ++++++++++++++++--------------
drivers/accel/qaic/qaic_debugfs.c | 4 +-
drivers/accel/qaic/qaic_drv.c | 16 +-
drivers/accel/qaic/qaic_fence.c | 173 ++++++++
drivers/accel/qaic/qaic_sched.c | 249 +++++++++++
include/uapi/drm/qaic_accel.h | 2 +-
10 files changed, 1001 insertions(+), 374 deletions(-)
create mode 100644 drivers/accel/qaic/qaic_fence.c
create mode 100644 drivers/accel/qaic/qaic_sched.c
base-commit: 0915fb19e08f7f14a03df78c67d081bbfa8ff1fa
--
2.43.0
