On 10/5/26 9:24 AM, Balaji Kalkonda wrote:
> Add device node for the DisplayPort controller, its OPP table, clocks
> and power domain, and connect it to the DPU and USB/DP QMP PHY.
>
> Signed-off-by: Balaji Kalkonda <[email protected]>
> ---
[...]
> + mdss_dp0: displayport-controller@9ad2000 {
> + compatible = "qcom,kaanapali-dp";
> + reg = <0x0 0x09ad2000 0x0 0x10c>,
> + <0x0 0x09ad2200 0x0 0xc8>,
> + <0x0 0x09ad3000 0x0 0x78>,
> + <0x0 0x09ad4000 0x0 0xa0>;
These register ranges are wider (most are 0x200)
Konrad
