Arm Core Local Accelerator (CLA) provides a CPU-local interface to accelerators that access memory through the local CPU's MMU. CLAs whose accelerators cannot be isolated from each other form an isolation domain.
Add a binding for arm,cla describing the register range, CPU association, DMA coherency and isolation domain. Document the privilege-level register frames, including reduced ranges exposed to virtual machines, and provide an example of two CLAs sharing a domain. Signed-off-by: Ryan Roberts <[email protected]> --- .../devicetree/bindings/misc/arm,cla.yaml | 77 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/arm,cla.yaml diff --git a/Documentation/devicetree/bindings/misc/arm,cla.yaml b/Documentation/devicetree/bindings/misc/arm,cla.yaml new file mode 100644 index 000000000000..b86a2befd09a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/arm,cla.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/arm,cla.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Core Local Accelerator (CLA) + +maintainers: + - Ryan Roberts <[email protected]> + +description: + A Core Local Accelerator (CLA) provides a CPU-local interface to up to eight + accelerators. The accelerators access memory through the local CPU's MMU. Each + CLA has its own register range, which can only be accessed by its local CPU. + Completion is polled through the registers; CLA does not generate interrupts. + +properties: + compatible: + const: arm,cla + + reg: + maxItems: 1 + description: + A single contiguous register range starting at the PL0 frame, aligned to + 256 KiB. Each privilege-level frame occupies 64 KiB, with PL0, PL1, PL2 + and PL3 at offsets 0, 0x10000, 0x20000 and 0x30000 respectively. The + complete range is 256 KiB. Higher-privilege frames may be omitted when + unavailable, for example in a virtual machine. The range must include at + least PL0 and PL1 when running at EL1 and additionally PL2 when running at + EL2. + + cpu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the CPU for which this CLA is local. Only that CPU can access + the CLA's registers. + + dma-coherent: true + + arm,domain: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Identifier of the CLA isolation domain. CLAs whose attached accelerators + cannot be isolated from each other, for example because they share an + inter-accelerator communication bus, must have the same domain ID. + Different isolation domains must have different IDs. IDs need not be + consecutive. A CLA that can be isolated from all other CLAs has its own + domain ID. + +required: + - compatible + - reg + - cpu + - dma-coherent + - arm,domain + +additionalProperties: false + +examples: + - | + /* Two CPU-local CLAs in the same isolation domain. */ + cla@10000000 { + compatible = "arm,cla"; + reg = <0x10000000 0x40000>; + cpu = <&cpu0>; + dma-coherent; + arm,domain = <0>; + }; + + cla@10040000 { + compatible = "arm,cla"; + reg = <0x10040000 0x40000>; + cpu = <&cpu1>; + dma-coherent; + arm,domain = <0>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 735f6527f920..98a25b3de9b4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2213,6 +2213,7 @@ ARM CORE LOCAL ACCELERATOR (CLA) DRIVER M: Ryan Roberts <[email protected]> L: [email protected] (moderated for non-subscribers) S: Supported +F: Documentation/devicetree/bindings/misc/arm,cla.yaml F: Documentation/misc-devices/arm-cla.rst F: drivers/misc/arm-cla/ -- 2.43.0
