From: Honglei Huang <[email protected]> Define the following ioctl structures and enums: - DRM_AMDGPU_GEM_SVM ioctl command and DRM_IOCTL_AMDGPU_GEM_SVM macro - enum amdgpu_ioctl_svm_op: SET_ATTR, GET_ATTR, RESET_ATTR operations - enum amdgpu_ioctl_svm_access: INACCESSIBLE, IN_PLACE, ALLOW_MIGRATE - enum amdgpu_ioctl_svm_location: SYSMEM, UNDEFINED, LOCAL, HIVE - enum amdgpu_ioctl_svm_attr_type: PREFERRED_LOC, PREFETCH_LOC, ACCESS, GRANULARITY, HOST_ACCESS, COHERENT, EXT_COHERENT, GPU_RO, GPU_EXEC, GPU_READ_MOSTLY - struct drm_amdgpu_svm_attribute: type and value pair - struct drm_amdgpu_gem_svm: ioctl payload with start_addr, size, operation, nattr, and attrs_ptr
Suggested-by: Christian König <[email protected]> Suggested-by: Huang Rui <[email protected]> Signed-off-by: Honglei Huang <[email protected]> --- include/uapi/drm/amdgpu_drm.h | 127 ++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index cd1b8034a2fb4..cfe463f2114a1 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -60,6 +60,7 @@ extern "C" { #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 #define DRM_AMDGPU_PROC_OPTIONS 0x1A #define DRM_AMDGPU_UALINK_HANDLE 0x1B +#define DRM_AMDGPU_GEM_SVM 0x1C #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -83,6 +84,9 @@ extern "C" { #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) #define DRM_IOCTL_AMDGPU_PROC_OPTIONS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options) #define DRM_IOCTL_AMDGPU_UALINK_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_UALINK_HANDLE, union drm_amdgpu_ualink_handle) +#define DRM_IOCTL_AMDGPU_GEM_SVM \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_SVM, \ + struct drm_amdgpu_gem_svm) /** * DOC: memory domains @@ -1735,6 +1739,129 @@ union drm_amdgpu_ualink_handle { union drm_amdgpu_ualink_handle_out out; }; +/** + * enum amdgpu_ioctl_svm_op - operation selector for DRM_IOCTL_AMDGPU_GEM_SVM. + * @AMDGPU_SVM_OP_SET_ATTR: apply the attributes in @attrs_ptr to the VA range + * [@start_addr, @start_addr + @size). + * @AMDGPU_SVM_OP_GET_ATTR: query the attributes at @start_addr. The caller + * lists the attribute types it is interested in via + * @attrs_ptr; the kernel fills in their current + * values and updates @size to the length of the + * contiguous range starting at @start_addr over + * which those values are constant. Input @size is an + * upper bound. This lets user space (e.g. CRIU) walk + * the address space and read back all attributes + * without knowing the range boundaries in advance. + * @AMDGPU_SVM_OP_RESET_ATTR: reset all attributes for the VA range to their + * default values. @attrs_ptr and @nattr are ignored. + */ +enum amdgpu_ioctl_svm_op { + AMDGPU_SVM_OP_SET_ATTR = 0, + AMDGPU_SVM_OP_GET_ATTR = 1, + AMDGPU_SVM_OP_RESET_ATTR = 2, +}; + +/** + * enum amdgpu_ioctl_svm_access - values for AMDGPU_SVM_ATTR_ACCESS. + * @AMDGPU_SVM_ACCESS_INACCESSIBLE: GPU must not access the range; any access + * is a fault. + * @AMDGPU_SVM_ACCESS_IN_PLACE: GPU may access the range only at its + * current backing store; the driver will + * never migrate pages to local VRAM. + * @AMDGPU_SVM_ACCESS_ALLOW_MIGRATE: GPU may access the range and the driver + * is allowed (but not required) to migrate + * pages between system memory and local + * VRAM to satisfy the preferred/prefetch + * location. + */ +enum amdgpu_ioctl_svm_access { + AMDGPU_SVM_ACCESS_INACCESSIBLE = 0, + AMDGPU_SVM_ACCESS_IN_PLACE = 1, + AMDGPU_SVM_ACCESS_ALLOW_MIGRATE = 2, +}; + +/** + * enum amdgpu_ioctl_svm_location - values for AMDGPU_SVM_ATTR_PREFERRED_LOC / + * AMDGPU_SVM_ATTR_PREFETCH_LOC. + * @AMDGPU_SVM_LOCATION_SYSMEM: back the range with system memory. + * @AMDGPU_SVM_LOCATION_UNDEFINED: no preference; the driver chooses. + * @AMDGPU_SVM_LOCATION_LOCAL: back the range with the local VRAM of the + * device the SVM context belongs to. + * @AMDGPU_SVM_LOCATION_HIVE: back the range with the VRAM of any device + * in the same XGMI hive as the local device. + * + * The location is expressed as a fixed enum rather than a device file + * descriptor on purpose: a descriptor has no stable meaning across a + * checkpoint/restore (CRIU) cycle. + */ +enum amdgpu_ioctl_svm_location { + AMDGPU_SVM_LOCATION_SYSMEM = 0, + AMDGPU_SVM_LOCATION_UNDEFINED = 1, + AMDGPU_SVM_LOCATION_LOCAL = 2, + AMDGPU_SVM_LOCATION_HIVE = 3, +}; + +/** + * enum amdgpu_ioctl_svm_attr_type - attribute selector for + * &drm_amdgpu_svm_attribute.type. + * + * @AMDGPU_SVM_ATTR_PREFERRED_LOC: Preferred backing location for the range. + * Value is one of &enum amdgpu_ioctl_svm_location. + * @AMDGPU_SVM_ATTR_PREFETCH_LOC: Prefetch target for the range. Value is + * one of &enum amdgpu_ioctl_svm_location. + * @AMDGPU_SVM_ATTR_ACCESS: GPU access policy for the range. Value is one + * of &enum amdgpu_ioctl_svm_access. + * @AMDGPU_SVM_ATTR_GRANULARITY: log2 of the migration granularity in pages. + * @AMDGPU_SVM_ATTR_HOST_ACCESS: Guarantee host access to memory. + * @AMDGPU_SVM_ATTR_COHERENT: Fine-grained coherency between all devices + * with access. + * @AMDGPU_SVM_ATTR_EXT_COHERENT: Fine-grained coherency between all devices + * using device-scope atomics. + * @AMDGPU_SVM_ATTR_GPU_RO: GPUs only read the range, allowing replication. + * @AMDGPU_SVM_ATTR_GPU_EXEC: Allow execution on GPU. + * @AMDGPU_SVM_ATTR_GPU_READ_MOSTLY: GPUs mostly read the range; may allow + * optimizations similar to GPU_RO, but writes still fault. + */ +enum amdgpu_ioctl_svm_attr_type { + AMDGPU_SVM_ATTR_PREFERRED_LOC = 0, + AMDGPU_SVM_ATTR_PREFETCH_LOC = 1, + AMDGPU_SVM_ATTR_ACCESS = 2, + AMDGPU_SVM_ATTR_GRANULARITY = 3, + /* Boolean attributes below: value must be 0 or 1. */ + AMDGPU_SVM_ATTR_HOST_ACCESS = 4, + AMDGPU_SVM_ATTR_COHERENT = 5, + AMDGPU_SVM_ATTR_EXT_COHERENT = 6, + AMDGPU_SVM_ATTR_GPU_RO = 7, + AMDGPU_SVM_ATTR_GPU_EXEC = 8, + AMDGPU_SVM_ATTR_GPU_READ_MOSTLY = 9, +}; + +/* One (type, value) pair carried by DRM_IOCTL_AMDGPU_GEM_SVM. */ +struct drm_amdgpu_svm_attribute { + /** AMDGPU_SVM_ATTR_* */ + __u32 type; + /** Attribute value; interpretation depends on @type */ + __u32 value; +}; + +/* Argument for DRM_IOCTL_AMDGPU_GEM_SVM. */ +struct drm_amdgpu_gem_svm { + /** Start of the virtual address range */ + __u64 start_addr; + /** + * Size of the range in bytes. For AMDGPU_SVM_OP_GET_ATTR this is an + * input upper bound and is updated on return to the length of the + * contiguous range starting at @start_addr with constant attributes. + */ + __u64 size; + /** AMDGPU_SVM_OP_* */ + __u32 operation; + /** Number of struct drm_amdgpu_svm_attribute entries in @attrs_ptr */ + __u32 nattr; + /** User pointer to an array of @nattr struct drm_amdgpu_svm_attribute */ + __u64 attrs_ptr; +}; + #if defined(__cplusplus) } #endif -- 2.53.0
