HDMI 2.0 asks the source to set TMDS_Bit_Clock_Ratio in the sink while the TMDS clock is stopped and to start the clock at least 1 ms later. vc4 writes the bit, and enables the scrambler, at the end of the enable sequence, long after the PHY has started, and clears it before the PHY stops. A sink that samples the bit when the clock appears never locks a 4K60 signal from a Raspberry Pi 5, while laptops that follow the order work on the same sink.
Patch 3 is the fix. Patch 1 is needed on BCM2712, where phy_disable() was an empty stub upstream, so the PHY kept running after disable; the Raspberry Pi tree has carried this since 2024. Patch 2 fixes a pre-existing race in the scrambling work cancel that the fix would otherwise make easier to hit. v1 was tested on a Raspberry Pi 5 running the Raspberry Pi 6.18 kernel with the same change applied, against the sink that showed the problem: plain enable at 4K60, 1080p60 to 4K60, 4K30 to 4K60, a sink reset and a sink power cycle all lock with zero character errors. v2 and v3 carry the same code; the hardware test of the final form is still pending and will be reported in this thread. Mainline was not booted on the Pi 5. The BCM2711 path is unchanged except for the enable order; I have no Pi 4 at hand. Changes in v3: - Patch 1: rewrote the commit message as requested. - Added Cc: [email protected] to all three patches as requested. - Collected the Reviewed-by tags on patches 2 and 3. - No code change since v2. - v2: https://lore.kernel.org/lkml/[email protected]/ Changes in v2: - Add Dom Cobley's vc6_hdmi_phy_disable() from the Raspberry Pi tree so the PHY really stops on BCM2712 before the SCDC bits are cleared. - Cancel the scrambling work unconditionally with cancel_delayed_work_sync(); the pending check skipped a running instance that then re-armed itself. - Enable the controller scrambler at the same point as the sink bits, before the PHY starts, instead of leaving it at the end of the enable sequence with the sink descrambler already on. - Drop the extra usleep_range(); drm_scdc_set_high_tmds_clock_ratio() already waits. - v1: https://lore.kernel.org/lkml/[email protected]/ Dom Cobley (1): drm/vc4: hdmi: power down the BCM2712 PHY when the output is disabled Lucas Tanure (2): drm/vc4: hdmi: always cancel the scrambling work synchronously drm/vc4: hdmi: enable scrambling before the TMDS clock starts drivers/gpu/drm/vc4/vc4_hdmi.c | 10 +++++----- drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 5 +++++ 2 files changed, 10 insertions(+), 5 deletions(-) -- 2.56.0
