On Wed, 14 Oct 2026 at 02:03, Cristian Ciocaltea <[email protected]> wrote: > > Historically, the HSM clock for BCM2835 was fixed at 163.7 MHz. Since > the pixel clock had to be at least 1% below the HSM clock, it was capped > at 162 MHz. > > Since commit cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate > depending on pixel rate"), the HSM clock rate is set to pixel clock * > 101 / 100. For a 165 MHz pixel clock, this gives an HSM rate of 166.65 > MHz, which, per Dave Stevenson, the hardware can handle without issues. > > Increase the max pixel clock to 165 MHz, which matches the maximum TMDS > character rate of HDMI 1.0 through 1.2. > > Suggested-by: Dave Stevenson <[email protected]> > Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Dave Stevenson <[email protected]> > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 0a95e14792e8..5b7dedd7a9a1 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -1319,7 +1319,7 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct > drm_encoder *encoder, > * users are able to use pixel clocks closer to HSM's, namely for > * 1920x1200@60Hz. So it was decided to have leave a 1% margin between > * both clocks. Which, for RPi0-3 implies a maximum pixel clock of > - * 162MHz. > + * 165MHz. > * > * Additionally, the AXI clock needs to be at least 25% of > * pixel clock, but HSM ends up being the limiting factor. > @@ -3190,7 +3190,7 @@ static const struct vc4_hdmi_variant bcm2835_variant = { > .encoder_type = VC4_ENCODER_TYPE_HDMI0, > .debugfs_name = "hdmi_regs", > .card_name = "vc4-hdmi", > - .max_pixel_clock = 162000000, > + .max_pixel_clock = HDMI_1_0_TMDS_CHAR_RATE_MAX_HZ, > .registers = vc4_hdmi_fields, > .num_registers = ARRAY_SIZE(vc4_hdmi_fields), > > > -- > 2.55.0 >
