From: Alessio Belle <[email protected]> This header file contains definitions common to all PowerVR architectures starting from Rogue, so rename both the file and its contents to reflect this.
Signed-off-by: Alessio Belle <[email protected]> Signed-off-by: Matt Coster <[email protected]> Signed-off-by: Alexandru Dadu <[email protected]> --- drivers/gpu/drm/imagination/pvr_fw_riscv.c | 14 +++---- .../gpu/drm/imagination/pvr_fw_riscv_internal.h | 43 ++++++++++++++++++++++ 2 files changed, 50 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c index 0d4dd45520a9..2b24c40bc20f 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c +++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c @@ -6,10 +6,10 @@ #include "pvr_fw_info.h" #include "pvr_fw_mips.h" #include "pvr_gem.h" +#define PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE +#include "pvr_fw_riscv_internal.h" +#undef PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE #include "pvr_rogue_cr_defs.h" -#define PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE -#include "pvr_rogue_riscv_internal.h" -#undef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE #include "pvr_vm.h" #include <linux/compiler.h> @@ -43,13 +43,13 @@ pvr_riscv_wrapper_init(struct pvr_device *pvr_dev) pvr_cr_write64(pvr_dev, PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG, - ROGUE_RISCV_REGION_BOOTLDR_CODE), + PVR_RISCV_REGION_BOOTLDR_CODE), code_addr | common_opts | ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_EN); pvr_cr_write64(pvr_dev, PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG, - ROGUE_RISCV_REGION_BOOTLDR_DATA), + PVR_RISCV_REGION_BOOTLDR_DATA), data_addr | common_opts | ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_LOAD_STORE_EN_EN); @@ -132,9 +132,9 @@ pvr_riscv_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) /* RISC-V cacheability is determined by address. */ if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED) - fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA); + fw_addr |= PVR_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA); else - fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_CACHED_DATA); + fw_addr |= PVR_RISCVFW_REGION_BASE(SHARED_CACHED_DATA); return fw_addr; } diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h b/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h new file mode 100644 index 000000000000..abcbb4ef06fe --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#ifndef PVR_FW_RISCV_INTERNAL_H +#define PVR_FW_RISCV_INTERNAL_H + +#ifndef PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE +#error This file may only be included if explicitly defined +#endif + +#include "pvr_rogue_cr_defs.h" + +#include <linux/bitops.h> +#include <linux/sizes.h> +#include <linux/types.h> + +#define PVR_RISCVFW_REGION_SIZE SZ_256M +#define PVR_RISCVFW_REGION_SHIFT __ffs(PVR_RISCVFW_REGION_SIZE) + +enum pvr_riscvfw_region { + PVR_RISCV_REGION__RESERVED_0 = 0, + PVR_RISCV_REGION__RESERVED_1, + PVR_RISCV_REGION_SOCIF, + PVR_RISCV_REGION__RESERVED_3, + PVR_RISCV_REGION__RESERVED_4, + PVR_RISCV_REGION_BOOTLDR_DATA, + PVR_RISCV_REGION_SHARED_CACHED_DATA, + PVR_RISCV_REGION__RESERVED_7, + PVR_RISCV_REGION_COREMEM, + PVR_RISCV_REGION__RESERVED_9, + PVR_RISCV_REGION__RESERVED_A, + PVR_RISCV_REGION__RESERVED_B, + PVR_RISCV_REGION_BOOTLDR_CODE, + PVR_RISCV_REGION_SHARED_UNCACHED_DATA, + PVR_RISCV_REGION__RESERVED_E, + PVR_RISCV_REGION__RESERVED_F, + + PVR_RISCV_REGION__COUNT, +}; + +#define PVR_RISCVFW_REGION_BASE(r) ((u32)(PVR_RISCV_REGION_##r) << PVR_RISCVFW_REGION_SHIFT) + +#endif /* PVR_FW_RISCV_INTERNAL_H */ -- 2.43.0
