On Fri, 30 Mar 2012 11:45:43 +0100 Chris Wilson <chris at chris-wilson.co.uk> wrote:
> On Fri, 30 Mar 2012 11:59:28 +0200, Jiri Slaby <jslaby at suse.cz> wrote: > > I don't know what to dump more, because iir is obviously zero too. What > > other sources of interrupts are on the (G33) chip? > > IIR is the master interrupt, with chained secondary interrupt statuses. > If IIR is 0, the interrupt wasn't raised by the GPU. I've actually seen cases where one of the PIPE*STAT regs is stuck, and even if IIR is 0 we still get interrupts... Jiri can you verify the PIPE*STAT regs have bits set, maybe one or more we don't check for? -- Jesse Barnes, Intel Open Source Technology Center -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20120409/f50f7a99/attachment.pgp>