From: Jayesh Choudhary <[email protected]> TI's AM62P and J722S SoCs support 2 display subsystems (DSS), DSS0 and DSS1, each with two video ports (VP) and two video planes. The outputs from the DSS VPs can be routed to two OLDI TXes (OLDI0, OLDI1), a DSI TX, or parallel DPI output.
DSS0 supports: - VP0: OLDI0 in single-link mode or OLDI0 and OLDI1 in dual-link or clone mode. - VP1: DPI DSS1 supports: - VP0: OLDI1 in single-link mode, or DPI - VP1: DPI or DSI The DSI is only connected to VP1 of DSS1, but OLDI and DPI are shared between the DSS instances. Thus only a single VP can output to DPI, and a single VP can use an OLDI block. Note that in single-link configuration OLDI0 can be used by DSS0, and at the same time OLDI1 can be used by DSS1. Add the necessary nodes to k3-am62p-j722s-common-main.dtsi, including DSS0, DSS1, OLDI0, OLDI1, DPHY and DSI. An important note about OLDIs: We have two OLDI hardware blocks. Each OLDI has certain configuration that has to be done before it can be used. The OLDI blocks get this configuration directly from the DSS block, via DSS registers. However, as a single OLDI block can be used either with DSS0 or DSS1, the source for the configuration changes according to (probably, this is unclear) a DSS related clock mux. So, afaics, when thinking about Linux device hierarchy wrt. control busses, OLDI blocks are children of DSS blocks, and they reside in a special DSS bus. And the OLDI parent changes according to the mux. As far as I know, there is no way we can represent this in the DT. Thus the solution used here (and in the driver) is that each DSS node contains the OLDI nodes that can be used with that DSS. Thus the DSS0 node has two child nodes, OLDI0 and OLDI1, and the DSS1 node has one child node, OLDI1. The OLDI1 nodes thus refer to the same piece of hardware, and they cannot be used at the same time. The selection which OLDI nodes to use are chosen in the board dts files, so assuming the dts files are correct, no resource conflict can happen. This is not a very nice solution, but the hardware doesn't make it easy to have a clean solution, and, most importantly, this works. Signed-off-by: Aradhya Bhatia <[email protected]> Signed-off-by: Jayesh Choudhary <[email protected]> Signed-off-by: Swamil Jain <[email protected]> [tomi.valkeinen: various fixes and improvements] Signed-off-by: Tomi Valkeinen <[email protected]> --- .../boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 110 +++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 20 ++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 16 +++ 3 files changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index f130c7cb998d..ae8db1bccadd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -64,6 +64,11 @@ audio_refclk1: clock-controller@82e4 { #clock-cells = <0>; }; + dss_oldi_io_ctrl: oldi-io-controller@8600 { + compatible = "ti,am625-dss-oldi-io-ctrl", "syscon"; + reg = <0x8600 0x200>; + }; + phy_gmii_sel: phy@4044 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4044 0x8>; @@ -1111,6 +1116,63 @@ dphy0: phy@30110000 { status = "disabled"; }; + dphy_tx0: phy@301c0000 { + compatible = "ti,j721e-dphy"; + reg = <0x0 0x301c0000 0x0 0x1000>; + clocks = <&k3_clks 238 16>, <&k3_clks 238 1>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 238 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 238 1>; + assigned-clock-parents = <&k3_clks 238 2>; + assigned-clock-rates = <25000000>; + status = "disabled"; + }; + + dss0: dss@30200000 { + compatible = "ti,am62p-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; /* DSS0 */ + clocks = <&k3_clks 186 6>, + <&dss0_vp1_clk>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + + dss0_oldi0: oldi@0 { + reg = <0>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; /* OLDI0_VD */ + status = "disabled"; + }; + + dss0_oldi1: oldi@1 { + reg = <1>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; /* OLDI1_VD */ + status = "disabled"; + }; + }; + }; + vpu: video-codec@30210000 { compatible = "ti,j721s2-wave521c", "cnm,wave521c"; reg = <0x00 0x30210000 0x00 0x10000>; @@ -1119,6 +1181,54 @@ vpu: video-codec@30210000 { power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; + dss1: dss@30220000 { + compatible = "ti,am62p-dss"; + reg = <0x00 0x30220000 0x00 0x1000>, /* common */ + <0x00 0x30222000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30226000 0x00 0x1000>, /* vid */ + <0x00 0x30227000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30228000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3022a000 0x00 0x1000>, /* vp1: Used for DPI/OLDI */ + <0x00 0x3022b000 0x00 0x1000>, /* vp2: Used for DPI/DSI */ + <0x00 0x30221000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 232 TI_SCI_PD_EXCLUSIVE>; /* DSS1 */ + clocks = <&k3_clks 232 8>, + <&dss1_vp1_clk>, + <&k3_clks 232 4>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + + dss1_oldi1: oldi@1 { + reg = <1>; + clocks = <&k3_clks 232 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; /* OLDI1_VD */ + status = "disabled"; + }; + }; + }; + + dsi0: dsi@30500000 { + compatible = "ti,j721e-dsi"; + reg = <0x0 0x30500000 0x0 0x100000>, <0x0 0x30270000 0x0 0x100>; + clocks = <&k3_clks 231 2>, <&k3_clks 231 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 231 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + hsm: remoteproc@43c00000 { compatible = "ti,hsm-m4fss"; /* contiguous regions but instantiated separately in HW */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index 9d6266d6ddb8..08541e615fb6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -89,9 +89,13 @@ cbass_main: bus@f0000 { <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ @@ -144,6 +148,22 @@ cbass_wakeup: bus@b00000 { }; }; + dss0_vp1_clk: clock-divider-oldi-dss0 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 186 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + + dss1_vp1_clk: clock-divider-oldi-dss1 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 232 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + #include "k3-am62p-j722s-common-thermal.dtsi" }; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index ca10c6904b69..dd04accfc518 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -228,6 +228,22 @@ cbass_wakeup: bus@b00000 { }; }; + dss0_vp1_clk: clock-divider-oldi-dss0 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 186 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + + dss1_vp1_clk: clock-divider-oldi-dss1 { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 232 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + #include "k3-am62p-j722s-common-thermal.dtsi" }; -- 2.43.0
