Hi Cristian, On Wed, 4 Nov 2026 at 20:56, Cristian Ciocaltea <[email protected]> wrote: > On 10/30/26 1:52 PM, Daniel Stone wrote: > > Same question as for the VOP2: why only special-case YUV422 when > > YUV420 also needs special treatment? And presumably in a way which > > can't just be mashed into bpc, because the maths doesn't work. So > > would this be better off being handled as a separate output-mode > > adjustment? > > For YUV420, the halving is already in the TMDS rate, so the PHY PLL output > equals the halved VOP2 DCLK - no special handling required here. > > However, since YUV422 is not deep-colour packed, its TMDS rate equals the > pixel > clock and therefore the PHY must get 8 bpc. This is essentially what > drm_hdmi_compute_mode_clock() does, forcing 8 for YUV422 for the same reason.
I don't follow 'deep-colour packed' as it seems like a non-sequitur. However, the TRM is pretty clear that a 2x pclk divisor on the clock rate is required for YUV420 and split-VOP display outputs, so this is fine. Cheers, Daniel
