On 11/6/2026 1:59 AM, Rob Clark wrote:
> From hw PoV, it's all part of the GPU. But from dt perspective it is
> it's own device with a separate io space. So we need to detect this and
> direct writes to the correct place.
>
> Acked-by: Konrad Dybcio <[email protected]>
> Tested-by: Alexander Koskovich <[email protected]> # Milos (Nothing Phone 3a)
> Signed-off-by: Rob Clark <[email protected]>
> ---
> drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> index a29f8149493c..59898b49a201 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> @@ -373,6 +373,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu)
> static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu;
> const struct a6xx_info *info = adreno_gpu->info->a6xx;
> const struct adreno_reglist_pipe *regs = info->nonctxt_reglist;
> unsigned int pipe_id, i;
> @@ -392,7 +393,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32
> *gmem_protect)
> if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT)
> *gmem_protect = regs[i].value;
>
> - gpu_write(gpu, regs[i].offset, regs[i].value);
> + if ((regs[i].offset << 2) >= gmu->mmio_offset) {
> + gmu_write(gmu, regs[i].offset, regs[i].value);
> + } else {
> + gpu_write(gpu, regs[i].offset, regs[i].value);
> + }
Any thoughts on a common IO accessor that can handle both gpu and gmu registers?
We had issues in the past where GMU offset was used with gpu_write(). We can
avoid
those confusions with a unified routine for both GPU and GMU registers.
Anyway, for this patch:
Reviewed-by: Akhil P Oommen <[email protected]>
-Akhil
> }
>
> a8xx_aperture_release(gpu, flags);
