Leif Delgass wrote:
On Thu, 6 Feb 2003, Brian Paul wrote:
The mask values indicate which bits in the pixel (word) correspond to each
color channel. The buffer size is the sum of the red, green, blue, and alpha
bits.
Mach64/R128
r g b a amask bsz ar ag ab aa Xvisual dpth
5 6 5 0 00000000 16 16 16 16 0 16
8 8 8 0 00000000 24 16 16 16 0 24
AFAIK, Mach64 doesn't support destination alpha. This looks correct.
Radeon/R200
r g b a amask bsz ar ag ab aa Xvisual dpth
5 6 5 0 00000000 16 16 16 16 0 16
8 8 8 8 ff000000 24 16 16 16 16 24
bufferSize should be set to 32 in radeon_dri.c
Shouldn't this be one of the following?
8 8 8 0 00000000 32 16 16 16 0 24
8 8 8 8 00000000 32 16 16 16 16 24
I know that in the XFree86 Radeon driver in 24-bit each pixel is
actually 4 bytes, whether the alpha channel is used or not.
MGA
r g b a amask bsz ar ag ab aa Xvisual dpth
5 6 5 0 00000000 16 16 16 16 0 16
8 8 8 8 00000000 32 16 16 16 0 24
alphaMask should be 0xff000000.
In the argb8888 READ_RGBA in mgaspan.c, alpha is always returned as 255.
One or the other of these is wrong.
Hmmm, I don't remember if the g200/400 supports dest alpha. The span
functions would seem to indicate "no".
8 8 8 8 00000000 32 16 16 16 16 24
GLINT
r g b a amask bsz ar ag ab aa Xvisual dpth
5 5 5 5 000f1000 16 16 16 16 0 15 (pScrn->depth)
8 8 8 0 00000000 32 16 16 16 0 24 (pScrn->depth)
This might be right.
Looks OK.
Shouldn't the buffer size be 24 here?
Ooops, yes.
tdfx
r g b a amask bsz ar ag ab aa Xvisual dpth
5 6 5 0 00000000 16 16 16 16 0 16
8 8 8 0 00000000 16 16 16 16 0 24 (pScrn->bitsPerPixel)
8 8 8 8 ff000000 16 16 16 16 16 32 (pScrn->bitsPerPixel)
8 8 8 0 00000000 32 16 16 16 0 24
8 8 8 8 00000000 32 16 16 16 16 24
In hw/drivers/tdfx/tdfx_dri.c bufferSize should be set to 32.
I'll check in corrections for these shortly. Thanks!
Sure. Could you also check these in on the mesa-4-0-4-branch?
Looks like Ian did.
-Brian
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