here is a new snapshot for R100 based cards
(only for testing, isn't ready for merging)
It seems to work ok with most apps I tested,
but it doesn't work for yuvrect.
Do we need the _radeon_render_stage or
should the _tnl_render_stage be enough?
best regards,
Andreas
Index: Mesa/src/mesa/drivers/dri/radeon/radeon_context.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_context.c,v
retrieving revision 1.20
diff -u -r1.20 radeon_context.c
--- Mesa/src/mesa/drivers/dri/radeon/radeon_context.c 11 Mar 2004 20:35:41 -0000
1.20
+++ Mesa/src/mesa/drivers/dri/radeon/radeon_context.c 21 Apr 2004 21:47:18 -0000
@@ -168,7 +168,7 @@
*/
&_radeon_texrect_stage,
- &_radeon_render_stage,
+/* &_radeon_render_stage, FIXME: disabled because of t_vertex.[ch] patch */
&_tnl_render_stage, /* FALLBACK: */
0,
};
Index: Mesa/src/mesa/drivers/dri/radeon/radeon_context.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_context.h,v
retrieving revision 1.12
diff -u -r1.12 radeon_context.h
--- Mesa/src/mesa/drivers/dri/radeon/radeon_context.h 12 Mar 2004 20:03:54 -0000
1.12
+++ Mesa/src/mesa/drivers/dri/radeon/radeon_context.h 21 Apr 2004 21:47:19 -0000
@@ -41,6 +41,7 @@
#ifdef GLX_DIRECT_RENDERING
#include <inttypes.h>
+#include "tnl/t_vertex.h"
#include "dri_util.h"
#include "drm.h"
#include "radeon_drm.h"
@@ -531,12 +532,13 @@
/* radeon_swtcl.c
*/
struct radeon_swtcl_info {
- GLuint SetupIndex;
- GLuint SetupNewInputs;
GLuint RenderIndex;
GLuint vertex_size;
- GLuint vertex_stride_shift;
GLuint vertex_format;
+
+ struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
+ GLuint vertex_attr_count;
+
GLubyte *verts;
/* Fallback rasterization functions
@@ -549,6 +551,18 @@
GLenum render_primitive;
GLuint numverts;
+ /**
+ * Offset of the 4UB color data within a hardware (swtcl) vertex.
+ */
+ GLuint coloroffset;
+
+ /**
+ * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
+ */
+ GLuint specoffset;
+
+ GLboolean needproj;
+
struct radeon_dma_region indexed_verts;
};
Index: Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c,v
retrieving revision 1.9
diff -u -r1.9 radeon_swtcl.c
--- Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c 27 Jan 2004 16:34:46 -0000
1.9
+++ Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c 21 Apr 2004 21:47:20 -0000
@@ -53,207 +53,150 @@
#include "radeon_swtcl.h"
#include "radeon_tcl.h"
-/***********************************************************************
- * Build render functions from dd templates *
- ***********************************************************************/
-
-
-#define RADEON_XYZW_BIT 0x01
-#define RADEON_RGBA_BIT 0x02
-#define RADEON_SPEC_BIT 0x04
-#define RADEON_TEX0_BIT 0x08
-#define RADEON_TEX1_BIT 0x10
-#define RADEON_PTEX_BIT 0x20
-#define RADEON_MAX_SETUP 0x40
static void flush_last_swtcl_prim( radeonContextPtr rmesa );
-static struct {
- void (*emit)( GLcontext *, GLuint, GLuint, void *, GLuint );
- interp_func interp;
- copy_pv_func copy_pv;
- GLboolean (*check_tex_sizes)( GLcontext *ctx );
- GLuint vertex_size;
- GLuint vertex_format;
-} setup_tab[RADEON_MAX_SETUP];
-
-
-#define TINY_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
- RADEON_CP_VC_FRMT_Z | \
- RADEON_CP_VC_FRMT_PKCOLOR)
-
-#define NOTEX_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
- RADEON_CP_VC_FRMT_Z | \
- RADEON_CP_VC_FRMT_W0 | \
- RADEON_CP_VC_FRMT_PKCOLOR | \
- RADEON_CP_VC_FRMT_PKSPEC)
-
-#define TEX0_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
- RADEON_CP_VC_FRMT_Z | \
- RADEON_CP_VC_FRMT_W0 | \
- RADEON_CP_VC_FRMT_PKCOLOR | \
- RADEON_CP_VC_FRMT_PKSPEC | \
- RADEON_CP_VC_FRMT_ST0)
-
-#define TEX1_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
- RADEON_CP_VC_FRMT_Z | \
- RADEON_CP_VC_FRMT_W0 | \
- RADEON_CP_VC_FRMT_PKCOLOR | \
- RADEON_CP_VC_FRMT_PKSPEC | \
- RADEON_CP_VC_FRMT_ST0 | \
- RADEON_CP_VC_FRMT_ST1)
-
-#define PROJ_TEX1_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
- RADEON_CP_VC_FRMT_Z | \
- RADEON_CP_VC_FRMT_W0 | \
- RADEON_CP_VC_FRMT_PKCOLOR | \
- RADEON_CP_VC_FRMT_PKSPEC | \
- RADEON_CP_VC_FRMT_ST0 | \
- RADEON_CP_VC_FRMT_Q0 | \
- RADEON_CP_VC_FRMT_ST1 | \
- RADEON_CP_VC_FRMT_Q1)
-
-#define TEX2_VERTEX_FORMAT 0
-#define TEX3_VERTEX_FORMAT 0
-#define PROJ_TEX3_VERTEX_FORMAT 0
-
-#define DO_XYZW (IND & RADEON_XYZW_BIT)
-#define DO_RGBA (IND & RADEON_RGBA_BIT)
-#define DO_SPEC (IND & RADEON_SPEC_BIT)
-#define DO_FOG (IND & RADEON_SPEC_BIT)
-#define DO_TEX0 (IND & RADEON_TEX0_BIT)
-#define DO_TEX1 (IND & RADEON_TEX1_BIT)
-#define DO_TEX2 0
-#define DO_TEX3 0
-#define DO_PTEX (IND & RADEON_PTEX_BIT)
-
-#define VERTEX radeonVertex
-#define VERTEX_COLOR radeon_color_t
-#define GET_VIEWPORT_MAT() 0
-#define GET_TEXSOURCE(n) n
-#define GET_VERTEX_FORMAT() RADEON_CONTEXT(ctx)->swtcl.vertex_format
-#define GET_VERTEX_STORE() RADEON_CONTEXT(ctx)->swtcl.verts
-#define GET_VERTEX_SIZE() RADEON_CONTEXT(ctx)->swtcl.vertex_size * sizeof(GLuint)
-
-#define HAVE_HW_VIEWPORT 1
-/* Tiny vertices don't seem to work atm - haven't looked into why.
- */
-#define HAVE_HW_DIVIDE (IND & ~(RADEON_XYZW_BIT|RADEON_RGBA_BIT))
-#define HAVE_TINY_VERTICES 1
-#define HAVE_RGBA_COLOR 1
-#define HAVE_NOTEX_VERTICES 1
-#define HAVE_TEX0_VERTICES 1
-#define HAVE_TEX1_VERTICES 1
-#define HAVE_TEX2_VERTICES 0
-#define HAVE_TEX3_VERTICES 0
-#define HAVE_PTEX_VERTICES 1
-#define CHECK_HW_DIVIDE (!(ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE| \
- DD_TRI_UNFILLED)))
+/***********************************************************************
+ * Initialization
+ ***********************************************************************/
-#define INTERP_VERTEX setup_tab[RADEON_CONTEXT(ctx)->swtcl.SetupIndex].interp
-#define COPY_PV_VERTEX setup_tab[RADEON_CONTEXT(ctx)->swtcl.SetupIndex].copy_pv
+#define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
+#define EMIT_ATTR( ATTR, STYLE, F0 ) \
+do { \
+ rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \
+ rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \
+ rmesa->swtcl.vertex_attr_count++; \
+ fmt_0 |= F0; \
+} while (0)
+#define EMIT_PAD( N ) \
+do { \
+ rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0;
\
+ rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD;
\
+ rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N);
\
+ rmesa->swtcl.vertex_attr_count++; \
+} while (0)
-/***********************************************************************
- * Generate pv-copying and translation functions *
- ***********************************************************************/
+static GLuint radeon_cp_vc_frmts[3][4] =
+{
+ { 0, 0, RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
+ { 0, 0, RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
+ { 0, 0, RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
+};
-#define TAG(x) radeon_##x
-#define IND ~0
-#include "tnl_dd/t_dd_vb.c"
-#undef IND
+static void radeonSetVertexFormat( GLcontext *ctx )
+{
+ radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+ TNLcontext *tnl = TNL_CONTEXT(ctx);
+ struct vertex_buffer *VB = &tnl->vb;
+ GLuint index = tnl->render_inputs;
+ int fmt_0 = 0;
+ int offset = 0;
-/***********************************************************************
- * Generate vertex emit and interp functions *
- ***********************************************************************/
+ /* Important:
+ */
+ if ( VB->NdcPtr != NULL ) {
+ VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
+ }
+ else {
+ VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
+ }
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT)
-#define TAG(x) x##_wg
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT)
-#define TAG(x) x##_wgt0
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_PTEX_BIT)
-#define TAG(x) x##_wgpt0
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT)
-#define TAG(x) x##_wgt0t1
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|\
- RADEON_PTEX_BIT)
-#define TAG(x) x##_wgpt0t1
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT)
-#define TAG(x) x##_wgfs
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|\
- RADEON_TEX0_BIT)
-#define TAG(x) x##_wgfst0
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|\
- RADEON_TEX0_BIT|RADEON_PTEX_BIT)
-#define TAG(x) x##_wgfspt0
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|\
- RADEON_TEX0_BIT|RADEON_TEX1_BIT)
-#define TAG(x) x##_wgfst0t1
-#include "tnl_dd/t_dd_vbtmp.h"
-
-#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|\
- RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_PTEX_BIT)
-#define TAG(x) x##_wgfspt0t1
-#include "tnl_dd/t_dd_vbtmp.h"
+ assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
+ rmesa->swtcl.vertex_attr_count = 0;
+ /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
+ * build up a hardware vertex.
+ */
+ if ( !rmesa->swtcl.needproj ) {
+ EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
+ RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
+ offset = 4;
+ }
+ else {
+ EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
+ RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
+ offset = 3;
+ }
+
+ rmesa->swtcl.coloroffset = offset;
+ EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
+ RADEON_CP_VC_FRMT_PKCOLOR );
+ offset += 1;
+
+ rmesa->swtcl.specoffset = 0;
+ if (index & (_TNL_BIT_COLOR1|_TNL_BIT_FOG)) {
+
+ if (index & _TNL_BIT_COLOR1) {
+ rmesa->swtcl.specoffset = offset;
+ EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
+ RADEON_CP_VC_FRMT_PKSPEC );
+ }
+ else {
+ EMIT_PAD( 3 );
+ }
-/***********************************************************************
- * Initialization
- ***********************************************************************/
+ if (index & _TNL_BIT_FOG) {
+ EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
+ RADEON_CP_VC_FRMT_PKSPEC );
+ }
+ else {
+ EMIT_PAD( 1 );
+ }
+ }
-static void init_setup_tab( void )
-{
- init_wg();
- init_wgt0();
- init_wgpt0();
- init_wgt0t1();
- init_wgpt0t1();
- init_wgfs();
- init_wgfst0();
- init_wgfspt0();
- init_wgfst0t1();
- init_wgfspt0t1();
-}
+ if (index & _TNL_BITS_TEX_ANY) {
+ int i;
+ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
+ if (index & _TNL_BIT_TEX(i)) {
+ GLuint sz = VB->TexCoordPtr[i]->size;
+ GLuint emit;
+ /* r200 doesn't like 1D or 4D texcoords (is that true?):
+ */
+ switch (sz) {
+ case 1:
+ case 2:
+ case 3: /* no attempt at cube texturing so far */
+ emit = EMIT_2F;
+ sz = 2;
+ break;
+ case 4:
+ emit = EMIT_3F_XYW;
+ sz = 3;
+ break;
+ default:
+ continue;
+ };
+
+ EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_SZ(sz),
+ radeon_cp_vc_frmts[i][sz] );
+ }
+ /* FIXME: does radeon/r200 support deactivated tmu0 but activated tmu1 ? */
+ }
+ }
-void radeonPrintSetupFlags(char *msg, GLuint flags )
-{
- fprintf(stderr, "%s(%x): %s%s%s%s%s%s\n",
- msg,
- (int)flags,
- (flags & RADEON_XYZW_BIT) ? " xyzw," : "",
- (flags & RADEON_RGBA_BIT) ? " rgba," : "",
- (flags & RADEON_SPEC_BIT) ? " spec/fog," : "",
- (flags & RADEON_TEX0_BIT) ? " tex-0," : "",
- (flags & RADEON_TEX1_BIT) ? " tex-1," : "",
- (flags & RADEON_PTEX_BIT) ? " proj-tex," : "");
+ if (fmt_0 != rmesa->swtcl.vertex_format) {
+ RADEON_NEWPRIM(rmesa);
+ rmesa->swtcl.vertex_format = fmt_0;
+ rmesa->swtcl.vertex_size =
+ _tnl_install_attrs( ctx,
+ rmesa->swtcl.vertex_attrs,
+ rmesa->swtcl.vertex_attr_count,
+ NULL, 0 );
+ rmesa->swtcl.vertex_size /= 4;
+ }
}
static void radeonRenderStart( GLcontext *ctx )
{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+#if 0
if (!setup_tab[rmesa->swtcl.SetupIndex].check_tex_sizes(ctx)) {
GLuint ind = rmesa->swtcl.SetupIndex |= (RADEON_PTEX_BIT|RADEON_RGBA_BIT);
@@ -271,89 +214,43 @@
tnl->Driver.Render.CopyPV = setup_tab[rmesa->swtcl.SetupIndex].copy_pv;
}
}
+#endif
+
+ radeonSetVertexFormat( ctx );
if (rmesa->dma.flush != 0 &&
rmesa->dma.flush != flush_last_swtcl_prim)
rmesa->dma.flush( rmesa );
}
-
-void radeonBuildVertices( GLcontext *ctx, GLuint start, GLuint count,
- GLuint newinputs )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- GLuint stride = rmesa->swtcl.vertex_size * sizeof(int);
- GLubyte *v = ((GLubyte *)rmesa->swtcl.verts + (start * stride));
-
- newinputs |= rmesa->swtcl.SetupNewInputs;
- rmesa->swtcl.SetupNewInputs = 0;
-
- if (!newinputs)
- return;
-
- setup_tab[rmesa->swtcl.SetupIndex].emit( ctx, start, count, v, stride );
-}
-
void radeonChooseVertexState( GLcontext *ctx )
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
- GLuint ind = (RADEON_XYZW_BIT | RADEON_RGBA_BIT);
-
- if (!rmesa->TclFallback || rmesa->Fallback)
- return;
- if (ctx->Fog.Enabled || (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR))
- ind |= RADEON_SPEC_BIT;
+ GLuint se_coord_fmt;
- if (ctx->Texture._EnabledUnits & 0x2)
- /* unit 1 enabled */
- ind |= RADEON_TEX0_BIT|RADEON_TEX1_BIT;
- else if (ctx->Texture._EnabledUnits & 0x1)
- /* unit 0 enabled */
- ind |= RADEON_TEX0_BIT;
-
- rmesa->swtcl.SetupIndex = ind;
-
- if (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED)) {
- tnl->Driver.Render.Interp = radeon_interp_extras;
- tnl->Driver.Render.CopyPV = radeon_copy_pv_extras;
+ /* HW perspective divide is a win, but tiny vertex formats are a
+ * bigger one.
+ */
+ if ( ((tnl->render_inputs & _TNL_BITS_TEX_ANY) == 0)
+ || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
+ rmesa->swtcl.needproj = GL_TRUE;
+ se_coord_fmt = (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
+ RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
+ RADEON_TEX1_W_ROUTING_USE_Q1);
}
else {
- tnl->Driver.Render.Interp = setup_tab[ind].interp;
- tnl->Driver.Render.CopyPV = setup_tab[ind].copy_pv;
- }
-
- if (setup_tab[ind].vertex_format != rmesa->swtcl.vertex_format) {
- RADEON_NEWPRIM(rmesa);
- rmesa->swtcl.vertex_format = setup_tab[ind].vertex_format;
- rmesa->swtcl.vertex_size = setup_tab[ind].vertex_size;
+ rmesa->swtcl.needproj = GL_FALSE;
+ se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
+ RADEON_TEX1_W_ROUTING_USE_Q1);
}
- {
- GLuint se_coord_fmt, needproj;
-
- /* HW perspective divide is a win, but tiny vertex formats are a
- * bigger one.
- */
- if (setup_tab[ind].vertex_format == TINY_VERTEX_FORMAT ||
- (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
- needproj = GL_TRUE;
- se_coord_fmt = (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
- RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
- RADEON_TEX1_W_ROUTING_USE_Q1);
- }
- else {
- needproj = GL_FALSE;
- se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
- RADEON_TEX1_W_ROUTING_USE_Q1);
- }
+ _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
- if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
- RADEON_STATECHANGE( rmesa, set );
- rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
- }
- _tnl_need_projected_coords( ctx, needproj );
+ if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
+ RADEON_STATECHANGE( rmesa, set );
+ rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
}
}
@@ -428,8 +325,11 @@
}
-
-
+#if 0
+/*******************************************************************************/
+/*******************************************************************************/
+/*******************************************************************************/
+/*******************************************************************************/
static void *radeon_emit_contiguous_verts( GLcontext *ctx,
GLuint start,
GLuint count,
@@ -670,6 +570,12 @@
radeon_run_render /* run */
};
+/*******************************************************************************/
+/*******************************************************************************/
+/*******************************************************************************/
+/*******************************************************************************/
+#endif
+
/**************************************************************************/
@@ -823,6 +729,18 @@
* Emit primitives as inline vertices *
***********************************************************************/
+#define HAVE_POINTS 1
+#define HAVE_LINES 1
+#define HAVE_LINE_STRIPS 1
+#define HAVE_TRIANGLES 1
+#define HAVE_TRI_STRIPS 1
+#define HAVE_TRI_STRIP_1 0
+#define HAVE_TRI_FANS 1
+#define HAVE_QUADS 0
+#define HAVE_QUAD_STRIPS 0
+#define HAVE_POLYGONS 0
+#define HAVE_ELTS 0
+
#undef LOCAL_VARS
#undef ALLOC_VERTS
#define CTX_ARG radeonContextPtr rmesa
@@ -904,20 +822,23 @@
#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
-#define VERT_SET_SPEC( v0, c ) \
+#define VERT_SET_SPEC( v, c ) \
do { \
- if (havespec) { \
- UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.red, (c)[0]); \
- UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.green, (c)[1]); \
- UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.blue, (c)[2]); \
+ if (specoffset) { \
+ radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
+ UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
+ UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
+ UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
} \
} while (0)
#define VERT_COPY_SPEC( v0, v1 ) \
do { \
- if (havespec) { \
- v0->v.specular.red = v1->v.specular.red; \
- v0->v.specular.green = v1->v.specular.green; \
- v0->v.specular.blue = v1->v.specular.blue; \
+ if (specoffset) { \
+ radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
+ radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
+ spec0->red = spec1->red; \
+ spec0->green = spec1->green; \
+ spec0->blue = spec1->blue; \
} \
} while (0)
@@ -926,8 +847,8 @@
*/
#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
-#define VERT_SAVE_SPEC( idx ) if (havespec) spec[idx] = v[idx]->ui[5]
-#define VERT_RESTORE_SPEC( idx ) if (havespec) v[idx]->ui[5] = spec[idx]
+#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
+#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
#undef LOCAL_VARS
#undef TAG
@@ -936,9 +857,9 @@
#define LOCAL_VARS(n) \
radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
GLuint color[n], spec[n]; \
- GLuint coloroffset = (rmesa->swtcl.vertex_size == 4 ? 3 : 4); \
- GLboolean havespec = (rmesa->swtcl.vertex_size > 4); \
- (void) color; (void) spec; (void) coloroffset; (void) havespec;
+ GLuint coloroffset = rmesa->swtcl.coloroffset; \
+ GLuint specoffset = rmesa->swtcl.specoffset; \
+ (void) color; (void) spec; (void) coloroffset; (void) specoffset;
/***********************************************************************
* Helpers for rendering unfilled primitives *
@@ -1149,7 +1070,11 @@
tnl->Driver.Render.Start = radeonRenderStart;
tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
tnl->Driver.Render.Finish = radeonRenderFinish;
- tnl->Driver.Render.BuildVertices = radeonBuildVertices;
+
+ tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
+ tnl->Driver.Render.CopyPV = _tnl_copy_pv;
+ tnl->Driver.Render.Interp = _tnl_interp;
+
tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
if (rmesa->TclFallback) {
@@ -1185,12 +1110,10 @@
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint size = TNL_CONTEXT(ctx)->vb.Size;
static int firsttime = 1;
if (firsttime) {
init_rast_tab();
- init_setup_tab();
firsttime = 0;
}
@@ -1198,9 +1121,14 @@
tnl->Driver.Render.Finish = radeonRenderFinish;
tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
- tnl->Driver.Render.BuildVertices = radeonBuildVertices;
+ tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
+ tnl->Driver.Render.CopyPV = _tnl_copy_pv;
+ tnl->Driver.Render.Interp = _tnl_interp;
- rmesa->swtcl.verts = (GLubyte *)ALIGN_MALLOC( size * 16 * 4, 32 );
+ _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
+ 22 * sizeof(GLfloat) ); /* FIXME: for 3TMUs
needs more */
+
+ rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
rmesa->swtcl.RenderIndex = ~0;
rmesa->swtcl.render_primitive = GL_TRIANGLES;
rmesa->swtcl.hw_primitive = 0;
@@ -1214,10 +1142,4 @@
if (rmesa->swtcl.indexed_verts.buf)
radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
__FUNCTION__ );
-
- if (rmesa->swtcl.verts) {
- ALIGN_FREE(rmesa->swtcl.verts);
- rmesa->swtcl.verts = 0;
- }
-
}
Index: Mesa/src/mesa/tnl/t_vertex.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/tnl/t_vertex.h,v
retrieving revision 1.6
diff -u -r1.6 t_vertex.h
--- Mesa/src/mesa/tnl/t_vertex.h 16 Feb 2004 15:15:24 -0000 1.6
+++ Mesa/src/mesa/tnl/t_vertex.h 21 Apr 2004 21:47:21 -0000
@@ -28,6 +28,8 @@
#ifndef _TNL_VERTEX_H
#define _TNL_VERTEX_H
+#include "mtypes.h"
+
/* New mechanism to specify hardware vertices so that tnl can build
* and manipulate them directly.
*/
@@ -46,10 +48,10 @@
EMIT_4F_VIEWPORT, /* do viewport transform and emit */
EMIT_3F_XYW, /* for projective texture */
EMIT_1UB_1F, /* for fog coordinate */
- EMIT_3UB_3F_BGR, /* for specular color */
EMIT_3UB_3F_RGB, /* for specular color */
- EMIT_4UB_4F_BGRA, /* for color */
+ EMIT_3UB_3F_BGR, /* for specular color */
EMIT_4UB_4F_RGBA, /* for color */
+ EMIT_4UB_4F_BGRA, /* for color */
EMIT_4CHAN_4F_RGBA, /* for swrast color */
EMIT_PAD, /* leave a hole of 'offset' bytes */
EMIT_MAX
