On Tue, 2004-05-25 at 21:55, Nicolai Haehnle wrote: 
> 
> As you may be aware, I was trying to get R300 support into a state where it 
> is possible to start OpenGL applications, let them hang the CP and *not* 
> bring  down the entire machine.
> 
> Looks like I was successful :)

Nice!

> The attached patch ati.unlock.1.patch against the DDX makes sure the RBBM 
> (whatever that means; I'm guessing Ring Buffer something or other) 

Register BackBone Manager.

> is reset in RADEONEngineReset(), before any other register is accessed that 
> could potentially cause a final crash (DSTCACHE_* is the major offender in this 
> category).
> 
> Now since I don't have any Radeon-related documentation at all, I have no 
> idea whether this patch will work on any other chip. For all that I know, 
> it might totally break the driver on R100/R200. 

Indeed, anyone who can reproduce a lockup with those chips should give
your patches a spin and let us know what effect they have.

> I'm especially confused by the fact that the bottom half of EngineReset() 
> treats RBBM_SOFT_RESET differently for the R300. Can anybody explain why?
> Maybe it would even be safest/cleanest to move the entire RBBM_SOFT_RESET 
> block to the top of the function?

I guess this code originates from Hui Yu and/or Kevin E. Martin, CC'ing
them. For their reference, I also paste the hunk in question:

--- ati-vladimir/radeon_accel.c 2004-05-20 16:02:24.000000000 +0200
+++ ati/radeon_accel.c  2004-05-25 21:14:24.000000000 +0200
@@ -170,6 +170,31 @@
     CARD32         rbbm_soft_reset;
     CARD32         host_path_cntl;
 
+    /* The following RBBM_SOFT_RESET sequence can help un-wedge
+     * an R300 after the command processor got stuck.
+     */
+    rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
+    OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+                                   RADEON_SOFT_RESET_CP |
+                                   RADEON_SOFT_RESET_HI |
+                                   RADEON_SOFT_RESET_SE |
+                                   RADEON_SOFT_RESET_RE |
+                                   RADEON_SOFT_RESET_PP |
+                                   RADEON_SOFT_RESET_E2 |
+                                   RADEON_SOFT_RESET_RB));
+    INREG(RADEON_RBBM_SOFT_RESET);
+    OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32)
+                                   ~(RADEON_SOFT_RESET_CP |
+                                     RADEON_SOFT_RESET_HI |
+                           


-- 
Earthling Michel DÃnzer      |     Debian (powerpc), X and DRI developer
Libre software enthusiast    |   http://svcs.affero.net/rm.php?r=daenzer



-------------------------------------------------------
This SF.Net email is sponsored by: Oracle 10g
Get certified on the hottest thing ever to hit the market... Oracle 10g. 
Take an Oracle 10g class now, and we'll give you the exam FREE.
http://ads.osdn.com/?ad_id=3149&alloc_id=8166&op=click
--
_______________________________________________
Dri-devel mailing list
[EMAIL PROTECTED]
https://lists.sourceforge.net/lists/listinfo/dri-devel

Reply via email to