Thomas Hellström wrote:
I just noticed that you are using a 2d BITBLT to temporarily stall the
command regulator for a moment.
I believe the XAA implementation in all current via 2d X server drivers
out there assume that they are reasonably alone in using the 2d engine and
that they expext that some registers are not changed by other
applications. This will probably at least break the accelerated X server
pixmap cache, unless used 2d engine registers are restored after the
BITBLT.
There is no way to restore registers since the existing values cannot be
determined when the commands are written. XAA code needs to make use
of the ring buffer or it will have to wait for engine idle when
switching between 2D and 3D. Also, 3D code cannot use the ring buffer
unless DDX calls the initialize ioctl. DDX needs to tell DRM where it
can perform this stall bitblt.
I plan to clean up the unichrome 2D driver with respect to this, but I'm
not sure when this will happen.
DRI code also uses the 2D engine. How does that work?
W respect to our previous discussion regarding the Mpeg2 decoder
I'll try programming it using the 2D commands. It might work.
Thanks for the info.
Is there any chance of having a command stream completion interrupt
implementation?
VIA said the hardware does not support it. It's strange that the older
Savage chips had command completion interrupt but not the newer Unichrome.
/Thomas
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