In fact, that was already discussed briefly at irc. For now it just seemed more important to get it working on more cards and fix the rendering problems than to worry about "minor" issues like multiple rendering apps :). I did get clearing only the needed tiles working (minus some off-by-one issues currently) though at least on my rv250 (with a 32x8 z pixel granularity however - for clearing the hardware seems to work on 8x2 4x4 "macro tiles", it looks like it might be even possible to get granularity down to 4x4 for clearing, at least on my card).Ok, here's the version which clears only the required tiles (with a 32x8 z-pixel granularity).
Works on rv250. It is almost certain to not work on non-rv cards (see code comments). I don't know if it works on rv100 cards, while the macro-tile size should be identical, the macro-tile shape may be not. Feedback might be helpful, especially if a pattern is visible which tiles are cleared and which not.
No new dri patch, use the old one.
Problems when only z or stencil buffer is cleared are unchanged (will probably look at it next), as is the problem with stencil/z readback (probably won't look at it soon...).
Roland
Index: shared/drm_pciids.txt
===================================================================
RCS file: /cvs/dri/drm/shared/drm_pciids.txt,v
retrieving revision 1.9
diff -u -r1.9 drm_pciids.txt
--- shared/drm_pciids.txt 7 Nov 2004 02:19:58 -0000 1.9
+++ shared/drm_pciids.txt 11 Nov 2004 20:00:19 -0000
@@ -1,35 +1,35 @@
[radeon]
-0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP "ATI Radeon RS100 IGP 320M"
-0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP "ATI Radeon RS200 IGP"
+0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS100 IGP 320M"
+0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS200 IGP"
0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500 Pro"
0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro"
0x1002 0x4146 CHIP_R300 "ATI Radeon AF 9700 Pro"
0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1/X1"
-0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600"
-0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600"
-0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600"
-0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9600 AS"
-0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2"
-0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2"
-0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
+0x1002 0x4150 CHIP_RV350|CHIP_IS_RV "ATI Radeon AP 9600"
+0x1002 0x4151 CHIP_RV350|CHIP_IS_RV "ATI Radeon AQ 9600"
+0x1002 0x4152 CHIP_RV350|CHIP_IS_RV "ATI Radeon AR 9600"
+0x1002 0x4153 CHIP_RV350|CHIP_IS_RV "ATI Radeon AS 9600 AS"
+0x1002 0x4154 CHIP_RV350|CHIP_IS_RV "ATI FireGL AT T2"
+0x1002 0x4156 CHIP_RV350|CHIP_IS_RV "ATI FireGL AV T2"
+0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS250 IGP"
0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
0x1002 0x4242 CHIP_R200 "ATI Radeon BC R200"
-0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100
Mobility U1"
-0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200
Mobility IGP 340M"
-0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250
Mobility IGP"
-0x1002 0x4964 CHIP_R250 "ATI Radeon Id R250 9000"
-0x1002 0x4965 CHIP_R250 "ATI Radeon Ie R250 9000"
-0x1002 0x4966 CHIP_R250 "ATI Radeon If R250 9000"
-0x1002 0x4967 CHIP_R250 "ATI Radeon Ig R250 9000"
+0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS100 Mobility U1"
+0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS200 Mobility IGP 340M"
+0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS250 Mobility IGP"
+0x1002 0x4964 CHIP_R250|CHIP_IS_RV "ATI Radeon Id R250 9000"
+0x1002 0x4965 CHIP_R250|CHIP_IS_RV "ATI Radeon Ie R250 9000"
+0x1002 0x4966 CHIP_R250|CHIP_IS_RV "ATI Radeon If R250 9000"
+0x1002 0x4967 CHIP_R250|CHIP_IS_RV "ATI Radeon Ig R250 9000"
0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500
M7"
0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL
7800 M7"
-0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6"
-0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6"
-0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Ld R250 Mobility 9000 M9"
-0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9"
-0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9"
-0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9"
-0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY "ATI Radeon RV300 Mobility 9600 M10"
+0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LY RV100
Mobility M6"
+0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LZ RV100
Mobility M6"
+0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Ld R250
Mobility 9000 M9"
+0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Le R250
Mobility 9000 M9"
+0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lf R250
Mobility 9000 M9"
+0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lg R250
Mobility 9000 M9"
+0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV350
Mobility 9600 M10"
0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100"
0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100"
0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100"
@@ -44,30 +44,30 @@
0x1002 0x514F CHIP_R200 "ATI Radeon QO R200 8500 LE"
0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500"
0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500"
-0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE"
-0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE"
+0x1002 0x5159 CHIP_RV100|CHIP_IS_RV "ATI Radeon QY RV100 7000/VE"
+0x1002 0x515A CHIP_RV100|CHIP_IS_RV "ATI Radeon QZ RV100 7000/VE"
0x1002 0x5168 CHIP_R200 "ATI Radeon Qh R200"
0x1002 0x5169 CHIP_R200 "ATI Radeon Qi R200"
0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200"
0x1002 0x516B CHIP_R200 "ATI Radeon Qk R200"
0x1002 0x516C CHIP_R200 "ATI Radeon Ql R200"
-0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300
Mobility IGP"
-0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5963 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5968 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5969 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596A CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596B CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c62 CHIP_RV280 "ATI Radeon RV280"
-0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c64 CHIP_RV280 "ATI Radeon RV280"
+0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS300 Mobility IGP"
+0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5960 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5961 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5962 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5963 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5964 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5968 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5969 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596A CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596B CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c62 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
+0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c64 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
[r128]
0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
Index: shared/radeon.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon.h,v
retrieving revision 1.33
diff -u -r1.33 radeon.h
--- shared/radeon.h 23 Oct 2004 06:25:56 -0000 1.33
+++ shared/radeon.h 11 Nov 2004 20:00:19 -0000
@@ -45,7 +45,7 @@
#define DRIVER_DATE "20020828"
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 12
+#define DRIVER_MINOR 13
#define DRIVER_PATCHLEVEL 0
/* Interface history:
@@ -82,6 +82,8 @@
* and GL_EXT_blend_[func|equation]_separate on r200
* 1.12- Add R300 CP microcode support - this just loads the CP on r300
* (No 3D support yet - just microcode loading).
+ * 1.13- Add packed R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
+ * - Added RADEON_CLEAR_HYPERZ flag to clear ioctl.
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
Index: shared/radeon_drm.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_drm.h,v
retrieving revision 1.24
diff -u -r1.24 radeon_drm.h
--- shared/radeon_drm.h 23 Oct 2004 06:25:56 -0000 1.24
+++ shared/radeon_drm.h 11 Nov 2004 20:00:19 -0000
@@ -145,7 +145,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
#define R200_EMIT_RB3D_BLENDCOLOR 76
-#define RADEON_MAX_STATE_PACKETS 77
+#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
+#define RADEON_MAX_STATE_PACKETS 78
/* Commands understood by cmd_buffer ioctl. More can be added but
@@ -193,6 +194,7 @@
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8
+#define RADEON_CLEAR_HYPERZ 0x8000000
/* Primitive types
*/
Index: shared/radeon_drv.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_drv.h,v
retrieving revision 1.37
diff -u -r1.37 radeon_drv.h
--- shared/radeon_drv.h 9 Nov 2004 00:54:19 -0000 1.37
+++ shared/radeon_drv.h 11 Nov 2004 20:00:19 -0000
@@ -68,6 +68,7 @@
CHIP_IS_IGP = 0x00020000UL,
CHIP_SINGLE_CRTC = 0x00040000UL,
CHIP_IS_AGP = 0x00080000UL,
+ CHIP_IS_RV = 0x00100000UL,
};
#define GET_RING_HEAD(dev_priv) DRM_READ32(
(dev_priv)->ring_rptr, 0 )
@@ -411,6 +412,7 @@
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
+#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
#define RADEON_RB3D_DEPTHPITCH 0x1c28
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
@@ -423,11 +425,15 @@
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
+# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
+# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@@ -535,7 +541,7 @@
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
-#define RADEON_RB3D_ZMASKOFFSET 0x1c34
+#define RADEON_RB3D_ZMASKOFFSET 0x3234
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
@@ -590,6 +596,8 @@
# define RADEON_3D_DRAW_IMMD 0x00002900
# define RADEON_3D_DRAW_INDX 0x00002A00
# define RADEON_3D_LOAD_VBPNTR 0x00002F00
+# define RADEON_3D_CLEAR_ZMASK 0x00003200
+# define RADEON_3D_CLEAR_HIZ 0x00003700
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
@@ -748,6 +756,8 @@
#define R200_RB3D_BLENDCOLOR 0x3218
+#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
+
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
Index: shared/radeon_state.c
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_state.c,v
retrieving revision 1.39
diff -u -r1.39 radeon_state.c
--- shared/radeon_state.c 23 Oct 2004 06:25:56 -0000 1.39
+++ shared/radeon_state.c 11 Nov 2004 20:00:19 -0000
@@ -205,6 +205,7 @@
case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
+ case R200_EMIT_TCL_POINT_SPRITE_CNTL:
/* These packets don't contain memory offsets */
break;
@@ -569,6 +570,7 @@
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
+ { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
};
@@ -780,11 +782,105 @@
}
}
+ /* hyper z clear */
+ if ( (flags & (RADEON_DEPTH | RADEON_STENCIL))&&(flags &
RADEON_CLEAR_HYPERZ ) ) {
+
+ int i;
+ int depthpixperline =
dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?
+ (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch /
4);
+
+ u32 clearmask;
+
+ u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
+ ((clear->depth_mask & 0xff) << 24);
+
+
+ /* Make sure we restore the 3D state next time.
+ * we haven't touched any "normal" state - still need this?
+ */
+ dev_priv->sarea_priv->ctx_owner = 0;
+
+ if (dev_priv->flags&CHIP_IS_RV) {
+ /* clear mask : chooses the clearing pattern.
+ could be used to clear only parts of macrotiles
+ (but that would get really complicated...)?
+ bit 0 and 1 (either or both of them ?!?!) are used to
+ not clear tile, bit 2 and 3 to not clear tile 1,..., at
+ least on rv250. Pattern is as follows:
+ | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
+ bits -------------------------------------------------
+ | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
+ */
+ clearmask = 0x0;
+ }
+ else {
+ /* FIXME : reverse engineer that for Rx00 cards */
+ clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f;
+ }
+
+ BEGIN_RING( 8 );
+ RADEON_WAIT_UNTIL_2D_IDLE();
+ OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE,
+ tempRB3D_DEPTHCLEARVALUE);
+ /* what offset is this exactly ? */
+ OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 );
+ /* need ctlstat, otherwise get some strange black flickering */
+ OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT,
RADEON_RB3D_ZC_FLUSH_ALL );
+ ADVANCE_RING();
+
+ for (i = 0; i < nbox; i++) {
+ int tileoffset, nrtilesx, nrtilesy, j;
+ if (dev_priv->flags&CHIP_IS_RV) {
+ /* find first macro tile (8x2 4x4 z-pixels) */
+ tileoffset = ((pbox[i].y1 >> 3) *
depthpixperline + pbox[i].x1) >> 5;
+ nrtilesx = ((pbox[i].x2 & ~31) - (pbox[i].x1 &
~31)) >> 5;
+ nrtilesy = ((pbox[i].y2 & ~7) - (pbox[i].y1 &
~7)) >> 3;
+ }
+ else {
+ /* FIXME : figure this out for non-rv cards!
+ nr of tiles cleared is likely only half what it
should be,
+ need more either vertically or horizontally (with
according offsets) */
+ tileoffset = ((pbox[i].y1 >> 3) *
depthpixperline + pbox[i].x1) >> 5;
+ nrtilesx = ((pbox[i].x2 & ~31) - (pbox[i].x1 &
~31)) >> 5;
+ nrtilesy = ((pbox[i].y2 & ~7) - (pbox[i].y1 &
~7)) >> 3;
+ }
+
+ for (j = 0; j <= nrtilesy; j++) {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2
) );
+ /* first tile */
+ /* judging by the first tile offset needed,
could possibly
+ directly address/clear 4x4 tiles instead of
8x2 * 4x4
+ macro tiles, though would still need clear
mask for
+ right/bottom if truely 4x4 granularity is
desired ? */
+ OUT_RING( tileoffset * 16 );
+ /* the number of tiles to clear */
+ OUT_RING( nrtilesx + 1);
+ /* clear mask : chooses the clearing pattern. */
+ OUT_RING( clearmask );
+ ADVANCE_RING();
+ tileoffset += depthpixperline >> 5;
+ }
+ }
+
+ /* TODO don't always clear all hi-level z tiles */
+ if
((!(dev_priv->flags&CHIP_IS_RV))&&(dev_priv->microcode_version==UCODE_R200))
+ /* r100 and cards without hierarchical z-buffer have no
high-level z-buffer */
+ {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
+ OUT_RING( 0x0 ); /* First tile */
+ OUT_RING( 0x3cc0 );
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ ADVANCE_RING();
+ }
+ }
+
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
* make sure the 3D engine is configured correctly.
*/
- if ( (dev_priv->microcode_version==UCODE_R200) &&
+ else if ( (dev_priv->microcode_version==UCODE_R200) &&
(flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
int tempPP_CNTL;
Index: shared-core/drm_pciids.txt
===================================================================
RCS file: /cvs/dri/drm/shared-core/drm_pciids.txt,v
retrieving revision 1.11
diff -u -r1.11 drm_pciids.txt
--- shared-core/drm_pciids.txt 7 Nov 2004 02:19:58 -0000 1.11
+++ shared-core/drm_pciids.txt 11 Nov 2004 20:00:19 -0000
@@ -1,35 +1,35 @@
[radeon]
-0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP "ATI Radeon RS100 IGP 320M"
-0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP "ATI Radeon RS200 IGP"
+0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS100 IGP 320M"
+0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS200 IGP"
0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500 Pro"
0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro"
0x1002 0x4146 CHIP_R300 "ATI Radeon AF 9700 Pro"
0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1/X1"
-0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600"
-0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600"
-0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600"
-0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9600 AS"
-0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2"
-0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2"
-0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
+0x1002 0x4150 CHIP_RV350|CHIP_IS_RV "ATI Radeon AP 9600"
+0x1002 0x4151 CHIP_RV350|CHIP_IS_RV "ATI Radeon AQ 9600"
+0x1002 0x4152 CHIP_RV350|CHIP_IS_RV "ATI Radeon AR 9600"
+0x1002 0x4153 CHIP_RV350|CHIP_IS_RV "ATI Radeon AS 9600 AS"
+0x1002 0x4154 CHIP_RV350|CHIP_IS_RV "ATI FireGL AT T2"
+0x1002 0x4156 CHIP_RV350|CHIP_IS_RV "ATI FireGL AV T2"
+0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS250 IGP"
0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
0x1002 0x4242 CHIP_R200 "ATI Radeon BC R200"
-0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100
Mobility U1"
-0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200
Mobility IGP 340M"
-0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250
Mobility IGP"
-0x1002 0x4964 CHIP_R250 "ATI Radeon Id R250 9000"
-0x1002 0x4965 CHIP_R250 "ATI Radeon Ie R250 9000"
-0x1002 0x4966 CHIP_R250 "ATI Radeon If R250 9000"
-0x1002 0x4967 CHIP_R250 "ATI Radeon Ig R250 9000"
+0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS100 Mobility U1"
+0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS200 Mobility IGP 340M"
+0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS250 Mobility IGP"
+0x1002 0x4964 CHIP_R250|CHIP_IS_RV "ATI Radeon Id R250 9000"
+0x1002 0x4965 CHIP_R250|CHIP_IS_RV "ATI Radeon Ie R250 9000"
+0x1002 0x4966 CHIP_R250|CHIP_IS_RV "ATI Radeon If R250 9000"
+0x1002 0x4967 CHIP_R250|CHIP_IS_RV "ATI Radeon Ig R250 9000"
0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500
M7"
0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL
7800 M7"
-0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6"
-0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6"
-0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Ld R250 Mobility 9000 M9"
-0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9"
-0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9"
-0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9"
-0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY "ATI Radeon RV300 Mobility 9600 M10"
+0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LY RV100
Mobility M6"
+0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LZ RV100
Mobility M6"
+0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Ld R250
Mobility 9000 M9"
+0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Le R250
Mobility 9000 M9"
+0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lf R250
Mobility 9000 M9"
+0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lg R250
Mobility 9000 M9"
+0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV350
Mobility 9600 M10"
0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100"
0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100"
0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100"
@@ -44,30 +44,30 @@
0x1002 0x514F CHIP_R200 "ATI Radeon QO R200 8500 LE"
0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500"
0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500"
-0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE"
-0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE"
+0x1002 0x5159 CHIP_RV100|CHIP_IS_RV "ATI Radeon QY RV100 7000/VE"
+0x1002 0x515A CHIP_RV100|CHIP_IS_RV "ATI Radeon QZ RV100 7000/VE"
0x1002 0x5168 CHIP_R200 "ATI Radeon Qh R200"
0x1002 0x5169 CHIP_R200 "ATI Radeon Qi R200"
0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200"
0x1002 0x516B CHIP_R200 "ATI Radeon Qk R200"
0x1002 0x516C CHIP_R200 "ATI Radeon Ql R200"
-0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300
Mobility IGP"
-0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5963 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5968 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5969 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596A CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596B CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c62 CHIP_RV280 "ATI Radeon RV280"
-0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c64 CHIP_RV280 "ATI Radeon RV280"
+0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS300 Mobility IGP"
+0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5960 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5961 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5962 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5963 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5964 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5968 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5969 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596A CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596B CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c62 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
+0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c64 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
[r128]
0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
Index: shared-core/radeon_drm.h
===================================================================
RCS file: /cvs/dri/drm/shared-core/radeon_drm.h,v
retrieving revision 1.25
diff -u -r1.25 radeon_drm.h
--- shared-core/radeon_drm.h 10 Oct 2004 05:52:19 -0000 1.25
+++ shared-core/radeon_drm.h 11 Nov 2004 20:00:19 -0000
@@ -144,7 +144,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
#define R200_EMIT_RB3D_BLENDCOLOR 76
-#define RADEON_MAX_STATE_PACKETS 77
+#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
+#define RADEON_MAX_STATE_PACKETS 78
/* Commands understood by cmd_buffer ioctl. More can be added but
* obviously these can't be removed or changed:
@@ -189,6 +190,7 @@
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8
+#define RADEON_CLEAR_HYPERZ 0x8000000
/* Primitive types
*/
Index: shared-core/radeon_drv.h
===================================================================
RCS file: /cvs/dri/drm/shared-core/radeon_drv.h,v
retrieving revision 1.38
diff -u -r1.38 radeon_drv.h
--- shared-core/radeon_drv.h 6 Nov 2004 16:55:41 -0000 1.38
+++ shared-core/radeon_drv.h 11 Nov 2004 20:00:20 -0000
@@ -78,10 +78,12 @@
* and GL_EXT_blend_[func|equation]_separate on r200
* 1.12- Add R300 CP microcode support - this just loads the CP on r300
* (No 3D support yet - just microcode loading).
+ * 1.13- Add packed R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
+ * - Added RADEON_CLEAR_HYPERZ flag to clear ioctl.
*/
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 12
+#define DRIVER_MINOR 13
#define DRIVER_PATCHLEVEL 0
enum radeon_family {
@@ -117,6 +119,7 @@
CHIP_IS_IGP = 0x00020000UL,
CHIP_SINGLE_CRTC = 0x00040000UL,
CHIP_IS_AGP = 0x00080000UL,
+ CHIP_IS_RV = 0x00100000UL,
};
#define GET_RING_HEAD(dev_priv) DRM_READ32(
(dev_priv)->ring_rptr, 0 )
@@ -466,6 +469,7 @@
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
+#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
#define RADEON_RB3D_DEPTHPITCH 0x1c28
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
@@ -478,11 +482,15 @@
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
+# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
+# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@@ -590,7 +598,7 @@
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
-#define RADEON_RB3D_ZMASKOFFSET 0x1c34
+#define RADEON_RB3D_ZMASKOFFSET 0x3234
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
@@ -644,6 +652,8 @@
# define RADEON_3D_DRAW_IMMD 0x00002900
# define RADEON_3D_DRAW_INDX 0x00002A00
# define RADEON_3D_LOAD_VBPNTR 0x00002F00
+# define RADEON_3D_CLEAR_ZMASK 0x00003200
+# define RADEON_3D_CLEAR_HIZ 0x00003700
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
@@ -801,6 +811,8 @@
#define R200_RB3D_BLENDCOLOR 0x3218
+#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
+
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
Index: shared-core/radeon_state.c
===================================================================
RCS file: /cvs/dri/drm/shared-core/radeon_state.c,v
retrieving revision 1.40
diff -u -r1.40 radeon_state.c
--- shared-core/radeon_state.c 6 Nov 2004 01:41:47 -0000 1.40
+++ shared-core/radeon_state.c 11 Nov 2004 20:00:22 -0000
@@ -271,6 +271,7 @@
case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
+ case R200_EMIT_TCL_POINT_SPRITE_CNTL:
/* These packets don't contain memory offsets */
break;
@@ -646,7 +647,9 @@
RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, {
RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, {
RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, {
-R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},};
+ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, {
+ R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
+};
/* ================================================================
* Performance monitoring functions
@@ -858,11 +861,106 @@
}
}
+ /* hyper z clear */
+ if ( (flags & (RADEON_DEPTH | RADEON_STENCIL))&&(flags &
RADEON_CLEAR_HYPERZ ) ) {
+
+ int i;
+ int depthpixperline =
dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?
+ (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch /
4);
+
+ u32 clearmask;
+
+ u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
+ ((clear->depth_mask & 0xff) << 24);
+
+
+ /* Make sure we restore the 3D state next time.
+ * we haven't touched any "normal" state - still need this?
+ */
+ dev_priv->sarea_priv->ctx_owner = 0;
+
+ if (dev_priv->flags&CHIP_IS_RV) {
+ /* clear mask : chooses the clearing pattern.
+ could be used to clear only parts of macrotiles
+ (but that would get really complicated...)?
+ bit 0 and 1 (either or both of them ?!?!) are used to
+ not clear tile, bit 2 and 3 to not clear tile 1,..., at
+ least on rv250. Pattern is as follows:
+ | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
+ bits -------------------------------------------------
+ | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
+ */
+ clearmask = 0x0;
+ }
+ else {
+ /* FIXME : reverse engineer that for Rx00 cards */
+ clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f;
+ }
+
+ BEGIN_RING( 8 );
+ RADEON_WAIT_UNTIL_2D_IDLE();
+ OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE,
+ tempRB3D_DEPTHCLEARVALUE);
+ /* what offset is this exactly ? */
+ OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 );
+ /* need ctlstat, otherwise get some strange black flickering */
+ OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT,
RADEON_RB3D_ZC_FLUSH_ALL );
+ ADVANCE_RING();
+
+ for (i = 0; i < nbox; i++) {
+ int tileoffset, nrtilesx, nrtilesy, j;
+ if (dev_priv->flags&CHIP_IS_RV) {
+ /* find first macro tile (8x2 4x4 z-pixels) */
+ tileoffset = ((pbox[i].y1 >> 3) *
depthpixperline + pbox[i].x1) >> 5;
+ nrtilesx = ((pbox[i].x2 & ~31) - (pbox[i].x1 &
~31)) >> 5;
+ nrtilesy = ((pbox[i].y2 & ~7) - (pbox[i].y1 &
~7)) >> 3;
+ }
+ else {
+ /* FIXME : figure this out for non-rv cards!
+ nr of tiles cleared is likely only half what it
should be,
+ need more either vertically or horizontally (with
according offsets) */
+ tileoffset = ((pbox[i].y1 >> 3) *
depthpixperline + pbox[i].x1) >> 5;
+ nrtilesx = ((pbox[i].x2 & ~31) - (pbox[i].x1 &
~31)) >> 5;
+ nrtilesy = ((pbox[i].y2 & ~7) - (pbox[i].y1 &
~7)) >> 3;
+ }
+
+ for (j = 0; j <= nrtilesy; j++) {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2
) );
+ /* first tile */
+ /* judging by the first tile offset needed,
could possibly
+ directly address/clear 4x4 tiles instead of
8x2 * 4x4
+ macro tiles, though would still need clear
mask for
+ right/bottom if truely 4x4 granularity is
desired ? */
+ OUT_RING( tileoffset * 16 );
+ /* the number of tiles to clear */
+ OUT_RING( nrtilesx + 1);
+ /* clear mask : chooses the clearing pattern. */
+ OUT_RING( clearmask );
+ ADVANCE_RING();
+ tileoffset += depthpixperline >> 5;
+ }
+ }
+
+ /* TODO don't always clear all hi-level z tiles */
+ if
((!(dev_priv->flags&CHIP_IS_RV))&&(dev_priv->microcode_version==UCODE_R200))
+ /* r100 and cards without hierarchical z-buffer have no
high-level z-buffer */
+ {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
+ OUT_RING( 0x0 ); /* First tile */
+ OUT_RING( 0x3cc0 );
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ ADVANCE_RING();
+ }
+ }
+
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
* make sure the 3D engine is configured correctly.
*/
- if ((dev_priv->microcode_version == UCODE_R200) && (flags &
(RADEON_DEPTH | RADEON_STENCIL))) {
+ else if ((dev_priv->microcode_version == UCODE_R200) &&
+ (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
int tempPP_CNTL;
int tempRE_CNTL;
