* need to check that we have enough of zbuffer/doublebuffer allocated to accomodate this..
What does everyone think ?
Wasn't the limit 2560x2560 with the r300 based chips? That's at least what
Maybe, I have not measured it. I only know it is less than 3000+ pixels that merged fb uses on my setup.
fglrx will do on r300. I'm wondering about that though a bit, that would be 11.3 bit for coords or so ;-). It would also mean the tiling regs need to be different a bit on r300 compared to r100/r200.
I looked through the register manual for Radeons and it looks like the did away with most of the tiling registers and options. For example, I don't think they have SURFACEx registers anymore - just a choice of tiling size, enable/disable and a "super-tiling" - probably used for multi-core rendering.
Of course, it might be the relevant registers just aren't there.
best
Vladimir Dergachev
Roland
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