On 10/31/07, Thomas Hellström <[EMAIL PROTECTED]> wrote:
> Dave Airlie wrote:
> > On 10/31/07, Thomas Hellström <[EMAIL PROTECTED]> wrote:
> >
> >> Dave,
> >>
> >> When starting out with TTM i did look a little at AGP caching issues and
> >> there was an issue with cached memory and speculative pre-fetching that
> >> may affect the mapped-cached memory,
> >> and that we need to know about but perhaps ignore.
> >>
> >> Suppose you bind a page to the AGP aperture, but don't change the kernel
> >> linear map caching policy.
> >> Then a speculatively prefetching processor may read the memory into its
> >> cache and then decide it doesn't
> >> want to use it, and actually write it back.
> >> Meanwhile the GPU may have changed the contents of the page and that
> >> change will be overwritten. Apparently there were big problems with AMD
> >> Athlons actually doing this. Linux people claiming it was an Athlon bug
> >> and AMD people claiming it was within specs.
> >>
> >>
> >
> > http://www.linuxjournal.com/files/linuxjournal.com/linuxjournal/articles/061/6148/6148s1.html
> >
> > Is what I believe you are talking about, I'll add something to the
> > comment mentioning this..
> >
> >
> Yup. In the end I believe the "change_page_attr(), global_flush_tlb()"
> sequence was the final outcome of this, but as I understand it,
> with your new code we never write through the GTT, which makes the only
> possible problem overwrites of GPU written data.
>

Well so far we've only dealt with Intel CPU/GPU combinations which
hopefully don't suffer from this issue.. I'll put a comment in but tbh
there are lots of ways to mess up things with the current APIs..

Try allocating a snooped batchbuffer, or a snooped private back buffer
or anything involved in a blit.... I'm going to add checks for some of
the more stupid things in the Intel superioctl code...

Dave.

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