On Wed, May 14, 2008 at 2:30 PM, Eric Anholt <[EMAIL PROTECTED]> wrote: > On Wed, 2008-05-14 at 02:33 +0200, Thomas Hellström wrote: > > > The real question is whether TTM suits the driver writers for use in > Linux > > > desktop and embedded environments, and I think so far I'm not seeing > > > enough positive feedback from the desktop side. > > > > > I actually haven't seen much feedback at all. At least not on the > > mailing lists. > > Anyway we need to look at the alternatives which currently is GEM. > > > > GEM, while still in development basically brings us back to the > > functionality of TTM 0.1, with added paging support but without > > fine-grained locking and caching policy support. > > > > I might have misunderstood things but quickly browsing the code raises > > some obvious questions: > > > > 1) Some AGP chipsets don't support page addresses > 32bits. GEM objects > > use GFP_HIGHUSER, and it's hardcoded into the linux swap code. > > The obvious solution here is what many DMA APIs do for IOMMUs that can't > address all of memory -- keep a pool of pages within the addressable > range and bounce data through them. I think the Linux kernel even has > interfaces to support us in this. Since it's not going to be a very > common case, we may not care about the performance. If we do find that > we care about the performance, we should first attempt to get what we > need into the linux kernel so we don't have to duplicate code, and only > if that fails do the duplication. > > I'm pretty sure the AGP chipsets versus >32-bits pages danger has been > overstated, though. Besides the fact that you needed to load one of > these older supposed machines with a full 4GB of memory (well, > theoretically 3.5GB but how often can you even boot a system with a 2, > 1, .5gb combo?), you also need a chipset that does >32-bit addressing. > > At least all AMD and Intel chipsets don't appear to have this problem in > the survey I did last night, as they've either got >32-bit chipset and > >32-bit gart, or 32-bit chipset and 32-bit gart. Basically all I'm > worried about is ATI PCI[E]GART at this point.
AMD PCIE and IGP GART support 40 bits (Dave just committed support this morning) so we should be fine on r3xx and newer PCIE cards. Alex ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
