Hi all,
(please Cc)
On Wed, 10 Dec 2008, Eric Anholt wrote:
> > There are two problems with this laptop: The first is that often (or
> > better always) when I start X and run it for some time (no idea what is
> > necessary), and then switch to the console the text mode is not
> > restored. The effect is that on the top of the screen there is probably
> > one of maybe two screen lines of the characters shown (screen lines
> > means 1 pixel lines) and the whole screen is flashing. The rest of the
> > screen is dark/grey and flashing.
[...]
> For the first issue, it's often hard to tell what's going wrong as the
> registers will be the same as far as we can see between success and
> failure. The difficulty of recovering text mode is one of the reasons
> that text mode is going away with kernel modesetting (planned for
> 2.6.29). intel_reg_dumper from the 2d driver build tree may help debug
> what's different between success and failure of vt switching today.
Ok, here are four times the output of intel_reg_dumper:
- intel-reg-in-X-pre-switch
Computer has booted, I am working in X and have *never* before
switched to the console
now I switch to the console which is garbled
- intel_console_bad
the command has been run on the console which was garbled
switching back to X and back to console gives me a working console
- intel_console_good
switching back to X and calling the dumper a last time in X
- intel-reg-in-X-after-fixed-switch
The diff between the two console dumps is quite small:
--- intel_console_bad 2008-12-17 22:18:39.000000000 +0100
+++ intel_console_good 2008-12-17 22:18:39.000000000 +0100
@@ -45,7 +45,7 @@
(II): FBC_COMMAND: 0x00000000
(II): FBC_STATUS: 0x00000000
(II): FBC_CONTROL2: 0x00000000
-(II): FBC_FENCE_OFF: 0x10000100
+(II): FBC_FENCE_OFF: 0x8202c500
(II): FBC_MOD_NUM: 0x00000000
(II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
@@ -166,10 +166,10 @@
(II): CR09: 0x4f
(II): CR0a: 0x0d
(II): CR0b: 0x0e
-(II): CR0c: 0x04
-(II): CR0d: 0x10
-(II): CR0e: 0x0b
-(II): CR0f: 0x90
+(II): CR0c: 0x00
+(II): CR0d: 0x50
+(II): CR0e: 0x07
+(II): CR0f: 0xd0
(II): CR10: 0x9c
(II): CR11: 0x8e
(II): CR12: 0x8f
but I have no way to interpret that.
Hope that helps.
BTW, is there anything about the other problem and the mal-detection of
an external monitor which caused gdm to start in a strange mode?
Best wishes
Norbert
-------------------------------------------------------------------------------
Dr. Norbert Preining <prein...@logic.at> Vienna University of Technology
Debian Developer <prein...@debian.org> Debian TeX Group
gpg DSA: 0x09C5B094 fp: 14DF 2E6C 0307 BE6D AD76 A9C0 D2BF 4AA3 09C5 B094
-------------------------------------------------------------------------------
WHAPLODE DROVE (n.)
A homicidal golf stroke.
--- Douglas Adams, The Meaning of Liff
(II): DumpRegsBegin
(II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
(II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 =
2)
(II): DPLL_TEST: 0x00010001 ()
(II): CACHE_MODE_0: 0x00006820
(II): D_STATE: 0x00000000
(II): DSPCLK_GATE_D: 0x1004000c (clock gates disabled: VRHUNIT DSSUNIT
OVRUNIT OVCUNIT)
(II): RENCLK_GATE_D1: 0x00000000
(II): RENCLK_GATE_D2: 0x000002c0
(II): SDVOB: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOUDI: 0x00000000
(II): DSPARB: 0x00000000
(II): DSPFW1: 0x3f8f0f0f
(II): DSPFW2: 0x150f0f0f
(II): DSPFW3: 0x00000000
(II): ADPA: 0x00000c00 (disabled, pipe A, -hsync, -vsync)
(II): LVDS: 0xc2008300 (enabled, pipe B, 18 bit, 1 channel)
(II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync,
-vsync)
(II): DVOB: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOA_SRCDIM: 0x00000000
(II): DVOB_SRCDIM: 0x00000000
(II): DVOC_SRCDIM: 0x00000000
(II): PP_CONTROL: 0x00000001 (power target: on)
(II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
(II): PFIT_CONTROL: 0x00000000
(II): PFIT_PGM_RATIOS: 0x071c0666
(II): PORT_HOTPLUG_EN: 0x00000120
(II): PORT_HOTPLUG_STAT: 0x00000400
(II): DSPACNTR: 0x58000400 (disabled, pipe A)
(II): DSPASTRIDE: 0x00001a00 (6656 bytes)
(II): DSPAPOS: 0x00000000 (0, 0)
(II): DSPASIZE: 0x00000000 (1, 1)
(II): DSPABASE: 0x00000000
(II): DSPASURF: 0x00100000
(II): DSPATILEOFF: 0x00000000
(II): PIPEACONF: 0x00000000 (disabled, inactive)
(II): PIPEASRC: 0x04ff03ff (1280, 1024)
(II): PIPEASTAT: 0x00000000 (status:)
(II): FBC_CFB_BASE: 0x00000000
(II): FBC_LL_BASE: 0x00000000
(II): FBC_CONTROL: 0x00000000
(II): FBC_COMMAND: 0x00000000
(II): FBC_STATUS: 0x00000000
(II): FBC_CONTROL2: 0x00000000
(II): FBC_FENCE_OFF: 0x8202c500
(II): FBC_MOD_NUM: 0x00000000
(II): FPA0: 0x00031305 (n = 3, m1 = 19, m2 = 5)
(II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_A: 0x14020003 (disabled, non-dvo, default clock,
DAC/serial mode, p1 = 2, p2 = 10)
(II): DPLL_A_MD: 0x00000000
(II): HTOTAL_A: 0x06af04ff (1280 active, 1712 total)
(II): HBLANK_A: 0x06af04ff (1280 start, 1712 end)
(II): HSYNC_A: 0x05d70557 (1368 start, 1496 end)
(II): VTOTAL_A: 0x044f03ff (1024 active, 1104 total)
(II): VBLANK_A: 0x044f03ff (1024 start, 1104 end)
(II): VSYNC_A: 0x04090402 (1027 start, 1034 end)
(II): BCLRPAT_A: 0x00000000
(II): VSYNCSHIFT_A: 0x00000000
(II): DSPBCNTR: 0xd9000400 (enabled, pipe B)
(II): DSPBSTRIDE: 0x00001a00 (6656 bytes)
(II): DSPBPOS: 0x00000000 (0, 0)
(II): DSPBSIZE: 0x00000000 (1, 1)
(II): DSPBBASE: 0x00000000
(II): DSPBSURF: 0x00100000
(II): DSPBTILEOFF: 0x00000000
(II): PIPEBCONF: 0xc0000000 (enabled, active)
(II): PIPEBSRC: 0x063f0383 (1600, 900)
(II): PIPEBSTAT: 0x00400206 (status: LBLC_EVENT_ENABLE
VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
(II): FPB0: 0x00030b06 (n = 3, m1 = 11, m2 = 6)
(II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_B: 0x98010000 (enabled, non-dvo, default clock, LVDS
mode, p1 = 1, p2 = 14)
(II): DPLL_B_MD: 0x00000000
(II): HTOTAL_B: 0x0727063f (1600 active, 1832 total)
(II): HBLANK_B: 0x0727063f (1600 start, 1832 end)
(II): HSYNC_B: 0x06bf067f (1664 start, 1728 end)
(II): VTOTAL_B: 0x038d0383 (900 active, 910 total)
(II): VBLANK_B: 0x038d0383 (900 start, 910 end)
(II): VSYNC_B: 0x03850384 (901 start, 902 end)
(II): BCLRPAT_B: 0x00000000
(II): VSYNCSHIFT_B: 0x00000000
(II): VCLK_DIVISOR_VGA0: 0x00031108
(II): VCLK_DIVISOR_VGA1: 0x00031406
(II): VCLK_POST_DIV: 0x00020002
(II): VGACNTRL: 0x80000000 (disabled)
(II): TV_CTL: 0x000c0010
(II): TV_DAC: 0x70000000
(II): TV_CSC_Y: 0x0332012d
(II): TV_CSC_Y2: 0x07d30104
(II): TV_CSC_U: 0x0733052d
(II): TV_CSC_U2: 0x05c70200
(II): TV_CSC_V: 0x0340030c
(II): TV_CSC_V2: 0x06d00200
(II): TV_CLR_KNOBS: 0x00606000
(II): TV_CLR_LEVEL: 0x010b00e1
(II): TV_H_CTL_1: 0x00400359
(II): TV_H_CTL_2: 0x80480022
(II): TV_H_CTL_3: 0x007c0344
(II): TV_V_CTL_1: 0x00f01415
(II): TV_V_CTL_2: 0x00060607
(II): TV_V_CTL_3: 0x80120001
(II): TV_V_CTL_4: 0x000900f0
(II): TV_V_CTL_5: 0x000a00f0
(II): TV_V_CTL_6: 0x000900f0
(II): TV_V_CTL_7: 0x000a00f0
(II): TV_SC_CTL_1: 0xc1710088
(II): TV_SC_CTL_2: 0x4e2d1dc8
(II): TV_SC_CTL_3: 0x00000000
(II): TV_WIN_POS: 0x00360024
(II): TV_WIN_SIZE: 0x02640198
(II): TV_FILTER_CTL_1: 0x8000085e
(II): TV_FILTER_CTL_2: 0x00028283
(II): TV_FILTER_CTL_3: 0x00014141
(II): TV_CC_CONTROL: 0x00000000
(II): TV_CC_DATA: 0x00000000
(II): TV_H_LUMA_0: 0xb1403000
(II): TV_H_LUMA_59: 0x0000b060
(II): TV_H_CHROMA_0: 0xb1403000
(II): TV_H_CHROMA_59: 0x0000b060
(II): MI_MODE: 0x00000200
(II): MI_ARB_STATE: 0x00000040
(II): MI_RDRET_STATE: 0x00000000
(II): ECOSKPD: 0x00000307
(II): SR00: 0x03
(II): SR01: 0x00
(II): SR02: 0x03
(II): SR03: 0x00
(II): SR04: 0x02
(II): SR05: 0x00
(II): SR06: 0x00
(II): SR07: 0x00
(II): MSR: 0x67
(II): ARX: 0x30
(II): AR00: 0x00
(II): AR01: 0x01
(II): AR02: 0x02
(II): AR03: 0x03
(II): AR04: 0x04
(II): AR05: 0x05
(II): AR06: 0x06
(II): AR07: 0x07
(II): AR08: 0x08
(II): AR09: 0x09
(II): AR0a: 0x0a
(II): AR0b: 0x0b
(II): AR0c: 0x0c
(II): AR0d: 0x0d
(II): AR0e: 0x0e
(II): AR0f: 0x0f
(II): AR10: 0x0c
(II): AR11: 0x00
(II): AR12: 0x0f
(II): AR13: 0x08
(II): AR14: 0x00
(II): CR00: 0x5f
(II): CR01: 0x4f
(II): CR02: 0x50
(II): CR03: 0x82
(II): CR04: 0x55
(II): CR05: 0x81
(II): CR06: 0xbf
(II): CR07: 0x1f
(II): CR08: 0x00
(II): CR09: 0x4f
(II): CR0a: 0x0d
(II): CR0b: 0x0e
(II): CR0c: 0x00
(II): CR0d: 0x00
(II): CR0e: 0x00
(II): CR0f: 0x00
(II): CR10: 0x9c
(II): CR11: 0x0e
(II): CR12: 0x8f
(II): CR13: 0x28
(II): CR14: 0x1f
(II): CR15: 0x96
(II): CR16: 0xb9
(II): CR17: 0xa3
(II): CR18: 0xff
(II): CR19: 0x00
(II): CR1a: 0x00
(II): CR1b: 0x00
(II): CR1c: 0x00
(II): CR1d: 0x00
(II): CR1e: 0x00
(II): CR1f: 0x00
(II): CR20: 0x00
(II): CR21: 0x00
(II): CR22: 0xfe
(II): CR23: 0x00
(II): CR24: 0x00
(II): SDVO phase shift 0 out of range -- probobly not an issue.
(II): pipe A dot 107520 n 3 m1 19 m2 5 p1 2 p2 10
(II): SDVO phase shift 0 out of range -- probobly not an issue.
(II): pipe B dot 100114 n 3 m1 11 m2 6 p1 1 p2 14
(II): DumpRegsEnd
(II): DumpRegsBegin
(II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
(II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 =
2)
(II): DPLL_TEST: 0x00010001 ()
(II): CACHE_MODE_0: 0x00006820
(II): D_STATE: 0x00000000
(II): DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
(II): RENCLK_GATE_D1: 0x00000000
(II): RENCLK_GATE_D2: 0x00000000
(II): SDVOB: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOUDI: 0x00000000
(II): DSPARB: 0x00000000
(II): DSPFW1: 0x3f8f0f0f
(II): DSPFW2: 0x150f0f0f
(II): DSPFW3: 0x00000000
(II): ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
(II): LVDS: 0xc2008300 (enabled, pipe B, 18 bit, 1 channel)
(II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync,
-vsync)
(II): DVOB: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOA_SRCDIM: 0x00000000
(II): DVOB_SRCDIM: 0x00000000
(II): DVOC_SRCDIM: 0x00000000
(II): PP_CONTROL: 0x00000001 (power target: on)
(II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
(II): PFIT_CONTROL: 0xa0000000
(II): PFIT_PGM_RATIOS: 0x071c0666
(II): PORT_HOTPLUG_EN: 0x00000120
(II): PORT_HOTPLUG_STAT: 0x00000400
(II): DSPACNTR: 0x00000000 (disabled, pipe A)
(II): DSPASTRIDE: 0x00000000 (0 bytes)
(II): DSPAPOS: 0x00000000 (0, 0)
(II): DSPASIZE: 0x00000000 (1, 1)
(II): DSPABASE: 0x00000000
(II): DSPASURF: 0x00000000
(II): DSPATILEOFF: 0x00000000
(II): PIPEACONF: 0x00000000 (disabled, inactive)
(II): PIPEASRC: 0x027f01df (640, 480)
(II): PIPEASTAT: 0x00000000 (status:)
(II): FBC_CFB_BASE: 0x00000000
(II): FBC_LL_BASE: 0x00000000
(II): FBC_CONTROL: 0x00000000
(II): FBC_COMMAND: 0x00000000
(II): FBC_STATUS: 0x00000000
(II): FBC_CONTROL2: 0x00000000
(II): FBC_FENCE_OFF: 0x10000100
(II): FBC_MOD_NUM: 0x00000000
(II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_A: 0x04020c00 (disabled, non-dvo, VGA, default clock,
DAC/serial mode, p1 = 2, p2 = 10)
(II): DPLL_A_MD: 0x00000003
(II): HTOTAL_A: 0x031f027f (640 active, 800 total)
(II): HBLANK_A: 0x03170287 (648 start, 792 end)
(II): HSYNC_A: 0x02ef028f (656 start, 752 end)
(II): VTOTAL_A: 0x020c01df (480 active, 525 total)
(II): VBLANK_A: 0x020401e7 (488 start, 517 end)
(II): VSYNC_A: 0x01eb01e9 (490 start, 492 end)
(II): BCLRPAT_A: 0x00000000
(II): VSYNCSHIFT_A: 0x00000000
(II): DSPBCNTR: 0x19000000 (disabled, pipe B)
(II): DSPBSTRIDE: 0x00000c80 (3200 bytes)
(II): DSPBPOS: 0x00000000 (0, 0)
(II): DSPBSIZE: 0x00000000 (1, 1)
(II): DSPBBASE: 0x00000000
(II): DSPBSURF: 0x00000000
(II): DSPBTILEOFF: 0x00000000
(II): PIPEBCONF: 0xc0000000 (enabled, active)
(II): PIPEBSRC: 0x027f018f (640, 400)
(II): PIPEBSTAT: 0x80000246 (status: FIFO_UNDERRUN VSYNC_INT_STATUS
LBLC_EVENT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
(II): FPB0: 0x00021305 (n = 2, m1 = 19, m2 = 5)
(II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_B: 0x98026c00 (enabled, non-dvo, spread spectrum
clock, LVDS mode, p1 = 2, p2 = 14)
(II): DPLL_B_MD: 0x00000003
(II): HTOTAL_B: 0x0727063f (1600 active, 1832 total)
(II): HBLANK_B: 0x0727063f (1600 start, 1832 end)
(II): HSYNC_B: 0x06bf067f (1664 start, 1728 end)
(II): VTOTAL_B: 0x038d0383 (900 active, 910 total)
(II): VBLANK_B: 0x038d0383 (900 start, 910 end)
(II): VSYNC_B: 0x03850384 (901 start, 902 end)
(II): BCLRPAT_B: 0x00000000
(II): VSYNCSHIFT_B: 0x00000000
(II): VCLK_DIVISOR_VGA0: 0x00031108
(II): VCLK_DIVISOR_VGA1: 0x00031406
(II): VCLK_POST_DIV: 0x00020002
(II): VGACNTRL: 0x22c4008e (enabled)
(II): TV_CTL: 0x000c0010
(II): TV_DAC: 0x70000000
(II): TV_CSC_Y: 0x0332012d
(II): TV_CSC_Y2: 0x07d30104
(II): TV_CSC_U: 0x0733052d
(II): TV_CSC_U2: 0x05c70200
(II): TV_CSC_V: 0x0340030c
(II): TV_CSC_V2: 0x06d00200
(II): TV_CLR_KNOBS: 0x00606000
(II): TV_CLR_LEVEL: 0x010b00e1
(II): TV_H_CTL_1: 0x00400359
(II): TV_H_CTL_2: 0x80480022
(II): TV_H_CTL_3: 0x007c0344
(II): TV_V_CTL_1: 0x00f01415
(II): TV_V_CTL_2: 0x00060607
(II): TV_V_CTL_3: 0x80120001
(II): TV_V_CTL_4: 0x000900f0
(II): TV_V_CTL_5: 0x000a00f0
(II): TV_V_CTL_6: 0x000900f0
(II): TV_V_CTL_7: 0x000a00f0
(II): TV_SC_CTL_1: 0xc1710088
(II): TV_SC_CTL_2: 0x4e2d1dc8
(II): TV_SC_CTL_3: 0x00000000
(II): TV_WIN_POS: 0x00360024
(II): TV_WIN_SIZE: 0x02640198
(II): TV_FILTER_CTL_1: 0x8000085e
(II): TV_FILTER_CTL_2: 0x00028283
(II): TV_FILTER_CTL_3: 0x00014141
(II): TV_CC_CONTROL: 0x00000000
(II): TV_CC_DATA: 0x00000000
(II): TV_H_LUMA_0: 0xb1403000
(II): TV_H_LUMA_59: 0x0000b060
(II): TV_H_CHROMA_0: 0xb1403000
(II): TV_H_CHROMA_59: 0x0000b060
(II): MI_MODE: 0x00000200
(II): MI_ARB_STATE: 0x00000040
(II): MI_RDRET_STATE: 0x00000000
(II): ECOSKPD: 0x00000307
(II): SR00: 0x03
(II): SR01: 0x00
(II): SR02: 0x03
(II): SR03: 0x00
(II): SR04: 0x02
(II): SR05: 0x00
(II): SR06: 0x00
(II): SR07: 0x00
(II): MSR: 0x67
(II): ARX: 0x30
(II): AR00: 0x00
(II): AR01: 0x01
(II): AR02: 0x02
(II): AR03: 0x03
(II): AR04: 0x04
(II): AR05: 0x05
(II): AR06: 0x06
(II): AR07: 0x07
(II): AR08: 0x08
(II): AR09: 0x09
(II): AR0a: 0x0a
(II): AR0b: 0x0b
(II): AR0c: 0x0c
(II): AR0d: 0x0d
(II): AR0e: 0x0e
(II): AR0f: 0x0f
(II): AR10: 0x0c
(II): AR11: 0x00
(II): AR12: 0x0f
(II): AR13: 0x08
(II): AR14: 0x00
(II): CR00: 0x5f
(II): CR01: 0x4f
(II): CR02: 0x50
(II): CR03: 0x82
(II): CR04: 0x55
(II): CR05: 0x81
(II): CR06: 0xbf
(II): CR07: 0x1f
(II): CR08: 0x00
(II): CR09: 0x4f
(II): CR0a: 0x0d
(II): CR0b: 0x0e
(II): CR0c: 0x04
(II): CR0d: 0x10
(II): CR0e: 0x0b
(II): CR0f: 0x90
(II): CR10: 0x9c
(II): CR11: 0x8e
(II): CR12: 0x8f
(II): CR13: 0x28
(II): CR14: 0x1f
(II): CR15: 0x96
(II): CR16: 0xb9
(II): CR17: 0xa3
(II): CR18: 0xff
(II): CR19: 0x00
(II): CR1a: 0x00
(II): CR1b: 0x00
(II): CR1c: 0x00
(II): CR1d: 0x00
(II): CR1e: 0x00
(II): CR1f: 0x00
(II): CR20: 0x00
(II): CR21: 0x00
(II): CR22: 0x20
(II): CR23: 0x00
(II): CR24: 0x00
(II): pipe A dot 100800 n 3 m1 17 m2 8 p1 2 p2 10
(II): pipe B dot 100000 n 2 m1 19 m2 5 p1 2 p2 14
(II): DumpRegsEnd
(II): DumpRegsBegin
(II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
(II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 =
2)
(II): DPLL_TEST: 0x00010001 ()
(II): CACHE_MODE_0: 0x00006820
(II): D_STATE: 0x00000000
(II): DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
(II): RENCLK_GATE_D1: 0x00000000
(II): RENCLK_GATE_D2: 0x00000000
(II): SDVOB: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOUDI: 0x00000000
(II): DSPARB: 0x00000000
(II): DSPFW1: 0x3f8f0f0f
(II): DSPFW2: 0x150f0f0f
(II): DSPFW3: 0x00000000
(II): ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
(II): LVDS: 0xc2008300 (enabled, pipe B, 18 bit, 1 channel)
(II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync,
-vsync)
(II): DVOB: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOA_SRCDIM: 0x00000000
(II): DVOB_SRCDIM: 0x00000000
(II): DVOC_SRCDIM: 0x00000000
(II): PP_CONTROL: 0x00000001 (power target: on)
(II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
(II): PFIT_CONTROL: 0xa0000000
(II): PFIT_PGM_RATIOS: 0x071c0666
(II): PORT_HOTPLUG_EN: 0x00000120
(II): PORT_HOTPLUG_STAT: 0x00000400
(II): DSPACNTR: 0x00000000 (disabled, pipe A)
(II): DSPASTRIDE: 0x00000000 (0 bytes)
(II): DSPAPOS: 0x00000000 (0, 0)
(II): DSPASIZE: 0x00000000 (1, 1)
(II): DSPABASE: 0x00000000
(II): DSPASURF: 0x00000000
(II): DSPATILEOFF: 0x00000000
(II): PIPEACONF: 0x00000000 (disabled, inactive)
(II): PIPEASRC: 0x027f01df (640, 480)
(II): PIPEASTAT: 0x00000000 (status:)
(II): FBC_CFB_BASE: 0x00000000
(II): FBC_LL_BASE: 0x00000000
(II): FBC_CONTROL: 0x00000000
(II): FBC_COMMAND: 0x00000000
(II): FBC_STATUS: 0x00000000
(II): FBC_CONTROL2: 0x00000000
(II): FBC_FENCE_OFF: 0x8202c500
(II): FBC_MOD_NUM: 0x00000000
(II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_A: 0x04020c00 (disabled, non-dvo, VGA, default clock,
DAC/serial mode, p1 = 2, p2 = 10)
(II): DPLL_A_MD: 0x00000003
(II): HTOTAL_A: 0x031f027f (640 active, 800 total)
(II): HBLANK_A: 0x03170287 (648 start, 792 end)
(II): HSYNC_A: 0x02ef028f (656 start, 752 end)
(II): VTOTAL_A: 0x020c01df (480 active, 525 total)
(II): VBLANK_A: 0x020401e7 (488 start, 517 end)
(II): VSYNC_A: 0x01eb01e9 (490 start, 492 end)
(II): BCLRPAT_A: 0x00000000
(II): VSYNCSHIFT_A: 0x00000000
(II): DSPBCNTR: 0x19000000 (disabled, pipe B)
(II): DSPBSTRIDE: 0x00000c80 (3200 bytes)
(II): DSPBPOS: 0x00000000 (0, 0)
(II): DSPBSIZE: 0x00000000 (1, 1)
(II): DSPBBASE: 0x00000000
(II): DSPBSURF: 0x00000000
(II): DSPBTILEOFF: 0x00000000
(II): PIPEBCONF: 0xc0000000 (enabled, active)
(II): PIPEBSRC: 0x027f018f (640, 400)
(II): PIPEBSTAT: 0x80000246 (status: FIFO_UNDERRUN VSYNC_INT_STATUS
LBLC_EVENT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
(II): FPB0: 0x00021305 (n = 2, m1 = 19, m2 = 5)
(II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_B: 0x98026c00 (enabled, non-dvo, spread spectrum
clock, LVDS mode, p1 = 2, p2 = 14)
(II): DPLL_B_MD: 0x00000003
(II): HTOTAL_B: 0x0727063f (1600 active, 1832 total)
(II): HBLANK_B: 0x0727063f (1600 start, 1832 end)
(II): HSYNC_B: 0x06bf067f (1664 start, 1728 end)
(II): VTOTAL_B: 0x038d0383 (900 active, 910 total)
(II): VBLANK_B: 0x038d0383 (900 start, 910 end)
(II): VSYNC_B: 0x03850384 (901 start, 902 end)
(II): BCLRPAT_B: 0x00000000
(II): VSYNCSHIFT_B: 0x00000000
(II): VCLK_DIVISOR_VGA0: 0x00031108
(II): VCLK_DIVISOR_VGA1: 0x00031406
(II): VCLK_POST_DIV: 0x00020002
(II): VGACNTRL: 0x22c4008e (enabled)
(II): TV_CTL: 0x000c0010
(II): TV_DAC: 0x70000000
(II): TV_CSC_Y: 0x0332012d
(II): TV_CSC_Y2: 0x07d30104
(II): TV_CSC_U: 0x0733052d
(II): TV_CSC_U2: 0x05c70200
(II): TV_CSC_V: 0x0340030c
(II): TV_CSC_V2: 0x06d00200
(II): TV_CLR_KNOBS: 0x00606000
(II): TV_CLR_LEVEL: 0x010b00e1
(II): TV_H_CTL_1: 0x00400359
(II): TV_H_CTL_2: 0x80480022
(II): TV_H_CTL_3: 0x007c0344
(II): TV_V_CTL_1: 0x00f01415
(II): TV_V_CTL_2: 0x00060607
(II): TV_V_CTL_3: 0x80120001
(II): TV_V_CTL_4: 0x000900f0
(II): TV_V_CTL_5: 0x000a00f0
(II): TV_V_CTL_6: 0x000900f0
(II): TV_V_CTL_7: 0x000a00f0
(II): TV_SC_CTL_1: 0xc1710088
(II): TV_SC_CTL_2: 0x4e2d1dc8
(II): TV_SC_CTL_3: 0x00000000
(II): TV_WIN_POS: 0x00360024
(II): TV_WIN_SIZE: 0x02640198
(II): TV_FILTER_CTL_1: 0x8000085e
(II): TV_FILTER_CTL_2: 0x00028283
(II): TV_FILTER_CTL_3: 0x00014141
(II): TV_CC_CONTROL: 0x00000000
(II): TV_CC_DATA: 0x00000000
(II): TV_H_LUMA_0: 0xb1403000
(II): TV_H_LUMA_59: 0x0000b060
(II): TV_H_CHROMA_0: 0xb1403000
(II): TV_H_CHROMA_59: 0x0000b060
(II): MI_MODE: 0x00000200
(II): MI_ARB_STATE: 0x00000040
(II): MI_RDRET_STATE: 0x00000000
(II): ECOSKPD: 0x00000307
(II): SR00: 0x03
(II): SR01: 0x00
(II): SR02: 0x03
(II): SR03: 0x00
(II): SR04: 0x02
(II): SR05: 0x00
(II): SR06: 0x00
(II): SR07: 0x00
(II): MSR: 0x67
(II): ARX: 0x30
(II): AR00: 0x00
(II): AR01: 0x01
(II): AR02: 0x02
(II): AR03: 0x03
(II): AR04: 0x04
(II): AR05: 0x05
(II): AR06: 0x06
(II): AR07: 0x07
(II): AR08: 0x08
(II): AR09: 0x09
(II): AR0a: 0x0a
(II): AR0b: 0x0b
(II): AR0c: 0x0c
(II): AR0d: 0x0d
(II): AR0e: 0x0e
(II): AR0f: 0x0f
(II): AR10: 0x0c
(II): AR11: 0x00
(II): AR12: 0x0f
(II): AR13: 0x08
(II): AR14: 0x00
(II): CR00: 0x5f
(II): CR01: 0x4f
(II): CR02: 0x50
(II): CR03: 0x82
(II): CR04: 0x55
(II): CR05: 0x81
(II): CR06: 0xbf
(II): CR07: 0x1f
(II): CR08: 0x00
(II): CR09: 0x4f
(II): CR0a: 0x0d
(II): CR0b: 0x0e
(II): CR0c: 0x00
(II): CR0d: 0x50
(II): CR0e: 0x07
(II): CR0f: 0xd0
(II): CR10: 0x9c
(II): CR11: 0x8e
(II): CR12: 0x8f
(II): CR13: 0x28
(II): CR14: 0x1f
(II): CR15: 0x96
(II): CR16: 0xb9
(II): CR17: 0xa3
(II): CR18: 0xff
(II): CR19: 0x00
(II): CR1a: 0x00
(II): CR1b: 0x00
(II): CR1c: 0x00
(II): CR1d: 0x00
(II): CR1e: 0x00
(II): CR1f: 0x00
(II): CR20: 0x00
(II): CR21: 0x00
(II): CR22: 0x20
(II): CR23: 0x00
(II): CR24: 0x00
(II): pipe A dot 100800 n 3 m1 17 m2 8 p1 2 p2 10
(II): pipe B dot 100000 n 2 m1 19 m2 5 p1 2 p2 14
(II): DumpRegsEnd
(II): DumpRegsBegin
(II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
(II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 =
2)
(II): DPLL_TEST: 0x00010001 ()
(II): CACHE_MODE_0: 0x00006820
(II): D_STATE: 0x00000000
(II): DSPCLK_GATE_D: 0x1004000c (clock gates disabled: VRHUNIT DSSUNIT
OVRUNIT OVCUNIT)
(II): RENCLK_GATE_D1: 0x00000000
(II): RENCLK_GATE_D2: 0x000002c0
(II): SDVOB: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not
detected)
(II): SDVOUDI: 0x00000000
(II): DSPARB: 0x00000000
(II): DSPFW1: 0x3f8f0f0f
(II): DSPFW2: 0x150f0f0f
(II): DSPFW3: 0x00000000
(II): ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
(II): LVDS: 0xc2008300 (enabled, pipe B, 18 bit, 1 channel)
(II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync,
-vsync)
(II): DVOB: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync,
+vsync)
(II): DVOA_SRCDIM: 0x00000000
(II): DVOB_SRCDIM: 0x00000000
(II): DVOC_SRCDIM: 0x00000000
(II): PP_CONTROL: 0x00000001 (power target: on)
(II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
(II): PFIT_CONTROL: 0x00000000
(II): PFIT_PGM_RATIOS: 0x071c0666
(II): PORT_HOTPLUG_EN: 0x00000120
(II): PORT_HOTPLUG_STAT: 0x00000400
(II): DSPACNTR: 0x00000000 (disabled, pipe A)
(II): DSPASTRIDE: 0x00000000 (0 bytes)
(II): DSPAPOS: 0x00000000 (0, 0)
(II): DSPASIZE: 0x00000000 (1, 1)
(II): DSPABASE: 0x00000000
(II): DSPASURF: 0x00000000
(II): DSPATILEOFF: 0x00000000
(II): PIPEACONF: 0x00000000 (disabled, inactive)
(II): PIPEASRC: 0x027f01df (640, 480)
(II): PIPEASTAT: 0x00000000 (status:)
(II): FBC_CFB_BASE: 0x00000000
(II): FBC_LL_BASE: 0x00000000
(II): FBC_CONTROL: 0x00000000
(II): FBC_COMMAND: 0x00000000
(II): FBC_STATUS: 0x00000000
(II): FBC_CONTROL2: 0x00000000
(II): FBC_FENCE_OFF: 0x10000100
(II): FBC_MOD_NUM: 0x00000000
(II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_A: 0x04020c00 (disabled, non-dvo, VGA, default clock,
DAC/serial mode, p1 = 2, p2 = 10)
(II): DPLL_A_MD: 0x00000003
(II): HTOTAL_A: 0x031f027f (640 active, 800 total)
(II): HBLANK_A: 0x03170287 (648 start, 792 end)
(II): HSYNC_A: 0x02ef028f (656 start, 752 end)
(II): VTOTAL_A: 0x020c01df (480 active, 525 total)
(II): VBLANK_A: 0x020401e7 (488 start, 517 end)
(II): VSYNC_A: 0x01eb01e9 (490 start, 492 end)
(II): BCLRPAT_A: 0x00000000
(II): VSYNCSHIFT_A: 0x00000000
(II): DSPBCNTR: 0xd9000400 (enabled, pipe B)
(II): DSPBSTRIDE: 0x00001a00 (6656 bytes)
(II): DSPBPOS: 0x00000000 (0, 0)
(II): DSPBSIZE: 0x00000000 (1, 1)
(II): DSPBBASE: 0x00000000
(II): DSPBSURF: 0x00100000
(II): DSPBTILEOFF: 0x00000000
(II): PIPEBCONF: 0xc0000000 (enabled, active)
(II): PIPEBSRC: 0x063f0383 (1600, 900)
(II): PIPEBSTAT: 0x00400206 (status: LBLC_EVENT_ENABLE
VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
(II): FPB0: 0x00030b06 (n = 3, m1 = 11, m2 = 6)
(II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II): DPLL_B: 0x98010000 (enabled, non-dvo, default clock, LVDS
mode, p1 = 1, p2 = 14)
(II): DPLL_B_MD: 0x00000000
(II): HTOTAL_B: 0x0727063f (1600 active, 1832 total)
(II): HBLANK_B: 0x0727063f (1600 start, 1832 end)
(II): HSYNC_B: 0x06bf067f (1664 start, 1728 end)
(II): VTOTAL_B: 0x038d0383 (900 active, 910 total)
(II): VBLANK_B: 0x038d0383 (900 start, 910 end)
(II): VSYNC_B: 0x03850384 (901 start, 902 end)
(II): BCLRPAT_B: 0x00000000
(II): VSYNCSHIFT_B: 0x00000000
(II): VCLK_DIVISOR_VGA0: 0x00031108
(II): VCLK_DIVISOR_VGA1: 0x00031406
(II): VCLK_POST_DIV: 0x00020002
(II): VGACNTRL: 0x80000000 (disabled)
(II): TV_CTL: 0x000c0010
(II): TV_DAC: 0x70000000
(II): TV_CSC_Y: 0x0332012d
(II): TV_CSC_Y2: 0x07d30104
(II): TV_CSC_U: 0x0733052d
(II): TV_CSC_U2: 0x05c70200
(II): TV_CSC_V: 0x0340030c
(II): TV_CSC_V2: 0x06d00200
(II): TV_CLR_KNOBS: 0x00606000
(II): TV_CLR_LEVEL: 0x010b00e1
(II): TV_H_CTL_1: 0x00400359
(II): TV_H_CTL_2: 0x80480022
(II): TV_H_CTL_3: 0x007c0344
(II): TV_V_CTL_1: 0x00f01415
(II): TV_V_CTL_2: 0x00060607
(II): TV_V_CTL_3: 0x80120001
(II): TV_V_CTL_4: 0x000900f0
(II): TV_V_CTL_5: 0x000a00f0
(II): TV_V_CTL_6: 0x000900f0
(II): TV_V_CTL_7: 0x000a00f0
(II): TV_SC_CTL_1: 0xc1710088
(II): TV_SC_CTL_2: 0x4e2d1dc8
(II): TV_SC_CTL_3: 0x00000000
(II): TV_WIN_POS: 0x00360024
(II): TV_WIN_SIZE: 0x02640198
(II): TV_FILTER_CTL_1: 0x8000085e
(II): TV_FILTER_CTL_2: 0x00028283
(II): TV_FILTER_CTL_3: 0x00014141
(II): TV_CC_CONTROL: 0x00000000
(II): TV_CC_DATA: 0x00000000
(II): TV_H_LUMA_0: 0xb1403000
(II): TV_H_LUMA_59: 0x0000b060
(II): TV_H_CHROMA_0: 0xb1403000
(II): TV_H_CHROMA_59: 0x0000b060
(II): MI_MODE: 0x00000200
(II): MI_ARB_STATE: 0x00000040
(II): MI_RDRET_STATE: 0x00000000
(II): ECOSKPD: 0x00000307
(II): SR00: 0x03
(II): SR01: 0x00
(II): SR02: 0x03
(II): SR03: 0x00
(II): SR04: 0x02
(II): SR05: 0x00
(II): SR06: 0x00
(II): SR07: 0x00
(II): MSR: 0x67
(II): ARX: 0x30
(II): AR00: 0x00
(II): AR01: 0x01
(II): AR02: 0x02
(II): AR03: 0x03
(II): AR04: 0x04
(II): AR05: 0x05
(II): AR06: 0x06
(II): AR07: 0x07
(II): AR08: 0x08
(II): AR09: 0x09
(II): AR0a: 0x0a
(II): AR0b: 0x0b
(II): AR0c: 0x0c
(II): AR0d: 0x0d
(II): AR0e: 0x0e
(II): AR0f: 0x0f
(II): AR10: 0x0c
(II): AR11: 0x00
(II): AR12: 0x0f
(II): AR13: 0x08
(II): AR14: 0x00
(II): CR00: 0x5f
(II): CR01: 0x4f
(II): CR02: 0x50
(II): CR03: 0x82
(II): CR04: 0x55
(II): CR05: 0x81
(II): CR06: 0xbf
(II): CR07: 0x1f
(II): CR08: 0x00
(II): CR09: 0x4f
(II): CR0a: 0x1f
(II): CR0b: 0x1e
(II): CR0c: 0x00
(II): CR0d: 0x00
(II): CR0e: 0x09
(II): CR0f: 0x6e
(II): CR10: 0x9c
(II): CR11: 0x8e
(II): CR12: 0x8f
(II): CR13: 0x28
(II): CR14: 0x1f
(II): CR15: 0x96
(II): CR16: 0xb9
(II): CR17: 0xa3
(II): CR18: 0xff
(II): CR19: 0x00
(II): CR1a: 0x00
(II): CR1b: 0x00
(II): CR1c: 0x00
(II): CR1d: 0x00
(II): CR1e: 0x00
(II): CR1f: 0x00
(II): CR20: 0x00
(II): CR21: 0x00
(II): CR22: 0x20
(II): CR23: 0x00
(II): CR24: 0x00
(II): pipe A dot 100800 n 3 m1 17 m2 8 p1 2 p2 10
(II): SDVO phase shift 0 out of range -- probobly not an issue.
(II): pipe B dot 100114 n 3 m1 11 m2 6 p1 1 p2 14
(II): DumpRegsEnd
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