On Wed, 2009-09-16 at 17:13 +1000, Dave Airlie wrote:
> 2009/9/16 Michel Dänzer <mic...@daenzer.net>:
> > On Wed, 2009-09-16 at 08:10 +1000, Dave Airlie wrote:
> >> 2009/9/16 Michel Dänzer <mic...@daenzer.net>:
> >> > From: Michel Dänzer <daen...@vmware.com>
> >> >
> >> > diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
> >> > index 2ba61e1..341c21a 100644
> >> > --- a/include/drm/radeon_drm.h
> >> > +++ b/include/drm/radeon_drm.h
> >> > @@ -802,11 +802,12 @@ struct drm_radeon_gem_create {
> >> > uint32_t flags;
> >> > };
> >> >
> >> > -#define RADEON_TILING_MACRO 0x1
> >> > -#define RADEON_TILING_MICRO 0x2
> >> > -#define RADEON_TILING_SWAP 0x4
> >> > -#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface
> >> > - * when mapped - i.e. front buffer */
> >> > +#define RADEON_TILING_MACRO 0x1
> >> > +#define RADEON_TILING_MICRO 0x2
> >> > +#define RADEON_TILING_SWAP_16BIT 0x4
> >> > +#define RADEON_TILING_SWAP_32BIT 0x8
> >> > +#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface
> >> > + * when mapped - i.e. front
> >> > buffer */
> >> >
> >>
> >> I know we haven't frozen API yet but this seems a bit unnecessary
> >> to reorder,
> >
> > Actually, I'm not sure what the problem is, AFAICT userspace doesn't use
> > the RADEON_TILING_SURFACE flag at all yet. (I know that's a bug, I have
> > a pending corresponding X driver patch that will fix it)
>
> Yeah I have code that uses it just not pushed out, we should be using it
> for front buffer allocs at least.
Right, below are the relevant parts of my X driver patch.
> >> do we really need swap 16 and 32 bit? does it not depend on other info
> >> about the buffer?
> >
> > A similar argument could be made against the separate macro / micro
> > tiling flags?
>
> Not really, you can't tell macro/micro without being told them, I thought
> the buffer bpp for swap would tell enough, we could pass it in if we
> aren't doing so, but if we aren't and we can't see any other need
> then two flags are fine.
radeon_bo_open() doesn't take the bpp, so the kernel can't really know
it. Also I suspect that the bpp alone without more information such as
formats won't be useful for other things, but it's hard to tell without
knowing what those other things would be.
So, is there anything left for me to do for this?
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index e6b948c..e8e14ae 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -915,6 +915,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int
height)
int screen_size;
int cpp = info->CurrentLayout.pixel_bytes;
struct radeon_bo *front_bo;
+ uint32_t tiling_flags = 0;
if (scrn->virtualX == width && scrn->virtualY == height)
return TRUE;
@@ -948,6 +950,22 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int
height)
if (!info->front_bo)
goto fail;
+ if (info->allowColorTiling)
+ tiling_flags |= RADEON_TILING_MACRO;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ switch (cpp) {
+ case 4:
+ tiling_flags |= RADEON_TILING_SWAP_32BIT;
+ break;
+ case 2:
+ tiling_flags |= RADEON_TILING_SWAP_16BIT;
+ break;
+ }
+#endif
+ if (tiling_flags)
+ radeon_bo_set_tiling(info->front_bo,
+ tiling_flags | RADEON_TILING_SURFACE, pitch *
cpp);
+
ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth,
scrn->bitsPerPixel, pitch * cpp,
info->front_bo->handle,
diff --git a/src/radeon_drm.h b/src/radeon_drm.h
index f974e19..49a5f81 100644
--- a/src/radeon_drm.h
+++ b/src/radeon_drm.h
@@ -802,9 +802,10 @@ struct drm_radeon_gem_create {
#define RADEON_TILING_MACRO 0x1
#define RADEON_TILING_MICRO 0x2
-#define RADEON_TILING_SWAP 0x4
-#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface
- * when mapped - i.e. front buffer */
+#define RADEON_TILING_SWAP_16BIT 0x4
+#define RADEON_TILING_SWAP_32BIT 0x8
+#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface
+ * when mapped - i.e. front buffer */
struct drm_radeon_gem_set_tiling {
uint32_t handle;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index faa0cfd..95247bb 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -855,6 +880,11 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
return FALSE;
}
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ radeon_bo_set_tiling(info->cursor_bo[c],
RADEON_TILING_SWAP_32BIT |
+ RADEON_TILING_SURFACE, stride);
+#endif
+
if (radeon_bo_map(info->cursor_bo[c], 1)) {
ErrorF("Failed to map cursor buffer memory\n");
}
@@ -875,6 +905,8 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
info->dri->textureSize = 0;
if (info->front_bo == NULL) {
+ uint32_t tiling_flags = 0;
+
info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,
0, RADEON_GEM_DOMAIN_VRAM, 0);
if (info->r600_shadow_fb == TRUE) {
@@ -883,8 +915,22 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
}
}
if (info->allowColorTiling) {
- radeon_bo_set_tiling(info->front_bo, RADEON_TILING_MACRO, stride);
+ tiling_flags |= RADEON_TILING_MACRO;
}
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ switch (cpp) {
+ case 4:
+ tiling_flags |= RADEON_TILING_SWAP_32BIT;
+ break;
+ case 2:
+ tiling_flags |= RADEON_TILING_SWAP_16BIT;
+ break;
+ }
+#endif
+ if (tiling_flags) {
+ radeon_bo_set_tiling(info->front_bo,
+ tiling_flags | RADEON_TILING_SURFACE, stride);
+ }
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n",
info->front_bo->size/1024);
--
Earthling Michel Dänzer | http://www.vmware.com
Libre software enthusiast | Debian, X and DRI developer
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