This patch simplify the GPU address space initialization,
it always try to put VRAM at same address as the VRAM PCI BAR
Sadly it seems that the memory controller of radeon got too
many bugs to safely put it at others place (especialy on IGP).
This patch also kill some duplicated value and split vram size
into 2 different value the mc_vram_size which will always be the
true VRAM size of the GPU (unless we hit the AGP corner case).
While vram_size is the amount of VRAM we will use (it can be less
than mc_vram_size if we limit the VRAM size or for matching the
aperture size).
This cleanup is done as first pass before adding support for
unmapped VRAM.
V2: Simplify things somemore, now all hw & AGP should work.
Signed-off-by: Jerome Glisse <jgli...@redhat.com>
---
drivers/gpu/drm/radeon/r100.c | 71 ++++---------
drivers/gpu/drm/radeon/r300.c | 8 +-
drivers/gpu/drm/radeon/r420.c | 26 +-----
drivers/gpu/drm/radeon/r520.c | 4 +-
drivers/gpu/drm/radeon/r600.c | 65 ++----------
drivers/gpu/drm/radeon/radeon.h | 27 ++++--
drivers/gpu/drm/radeon/radeon_agp.c | 2 +
drivers/gpu/drm/radeon/radeon_device.c | 154 ++++++++++++++++-----------
drivers/gpu/drm/radeon/radeon_fb.c | 6 +-
drivers/gpu/drm/radeon/radeon_gem.c | 4 +-
drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 2 +-
drivers/gpu/drm/radeon/radeon_test.c | 2 +-
drivers/gpu/drm/radeon/radeon_ttm.c | 19 ++--
drivers/gpu/drm/radeon/rs400.c | 16 +--
drivers/gpu/drm/radeon/rs600.c | 27 ++---
drivers/gpu/drm/radeon/rs690.c | 26 ++---
drivers/gpu/drm/radeon/rv515.c | 4 +-
drivers/gpu/drm/radeon/rv770.c | 45 ++-------
18 files changed, 196 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 824cc64..9676a7c 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -200,9 +200,8 @@ int r100_pci_gart_enable(struct radeon_device *rdev)
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
WREG32(RADEON_AIC_CNTL, tmp);
/* set address range for PCI address translate */
- WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
- WREG32(RADEON_AIC_HI_ADDR, tmp);
+ WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
+ WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
/* set PCI GART page-table base address */
WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
@@ -1881,44 +1880,25 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
uint32_t tom;
/* read NB_TOM to get the amount of ram stolen for the GPU */
tom = RREG32(RADEON_NB_TOM);
- rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1)
<< 16);
+ rdev->mc.mc_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) <<
16);
/* for IGPs we need to keep VRAM where it was put by the BIOS */
- rdev->mc.vram_location = (tom & 0xffff) << 16;
- WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
- rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
+ rdev->mc.vram_start = (tom & 0xffff) << 16;
+ WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.mc_vram_size);
} else {
- rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+ rdev->mc.mc_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
/* Some production boards of m6 will report 0
* if it's 8 MB
*/
- if (rdev->mc.real_vram_size == 0) {
- rdev->mc.real_vram_size = 8192 * 1024;
- WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
- }
- /* let driver place VRAM */
- rdev->mc.vram_location = 0xFFFFFFFFUL;
- /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
- * Novell bug 204882 + along with lots of ubuntu ones */
- if (config_aper_size > rdev->mc.real_vram_size)
- rdev->mc.mc_vram_size = config_aper_size;
- else
- rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
+ if (rdev->mc.mc_vram_size == 0) {
+ rdev->mc.mc_vram_size = 8192 * 1024;
+ WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.mc_vram_size);
+ }
}
-
/* work out accessible VRAM */
+ /* FIXME: take advantage of second aperture when it works */
accessible = r100_get_accessible_vram(rdev);
-
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
-
- if (accessible > rdev->mc.aper_size)
- accessible = rdev->mc.aper_size;
-
- if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
- rdev->mc.mc_vram_size = rdev->mc.aper_size;
-
- if (rdev->mc.real_vram_size > rdev->mc.aper_size)
- rdev->mc.real_vram_size = rdev->mc.aper_size;
}
void r100_vga_set_state(struct radeon_device *rdev, bool state)
@@ -1938,7 +1918,6 @@ void r100_vga_set_state(struct radeon_device *rdev, bool
state)
void r100_vram_info(struct radeon_device *rdev)
{
r100_vram_get_type(rdev);
-
r100_vram_init_sizes(rdev);
}
@@ -3168,10 +3147,10 @@ void r100_mc_stop(struct radeon_device *rdev, struct
r100_mc_save *save)
void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
{
/* Update base address for crtc */
- WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
+ WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
- rdev->mc.vram_location);
+ rdev->mc.vram_start);
}
/* Restore CRTC registers */
WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
@@ -3334,28 +3313,16 @@ void r100_fini(struct radeon_device *rdev)
int r100_mc_init(struct radeon_device *rdev)
{
int r;
- u32 tmp;
- /* Setup GPU memory space */
- rdev->mc.vram_location = 0xFFFFFFFFUL;
- rdev->mc.gtt_location = 0xFFFFFFFFUL;
- if (rdev->flags & RADEON_IS_IGP) {
- tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
- rdev->mc.vram_location = tmp << 16;
- }
if (rdev->flags & RADEON_IS_AGP) {
r = radeon_agp_init(rdev);
- if (r) {
- printk(KERN_WARNING "[drm] Disabling AGP\n");
- rdev->flags &= ~RADEON_IS_AGP;
- rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
- } else {
- rdev->mc.gtt_location = rdev->mc.agp_base;
- }
+ if (r)
+ return r;
+ radeon_mc_init_vram_location(rdev, rdev->mc.aper_base);
+ } else {
+ radeon_mc_init_vram_location(rdev, rdev->mc.aper_base);
+ radeon_mc_init_gtt_location(rdev);
}
- r = radeon_mc_setup(rdev);
- if (r)
- return r;
return 0;
}
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83378c3..509f6da 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -112,15 +112,15 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
/* discard memory request outside of configured range */
tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
- WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
+ WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
+ tmp = rdev->mc.gtt_end + 1 - RADEON_GPU_PAGE_SIZE;
WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
table_addr = rdev->gart.table_addr;
WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
/* FIXME: setup default page */
- WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
+ WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
/* Clear error */
WREG32_PCIE(0x18, 0);
@@ -1327,7 +1327,7 @@ int r300_init(struct radeon_device *rdev)
/* Get vram informations */
r300_vram_info(rdev);
/* Initialize memory controller (also test AGP) */
- r = r420_mc_init(rdev);
+ r = r100_mc_init(rdev);
if (r)
return r;
/* Fence driver */
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index c05a727..8418225 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -32,30 +32,6 @@
#include "atom.h"
#include "r420d.h"
-int r420_mc_init(struct radeon_device *rdev)
-{
- int r;
-
- /* Setup GPU memory space */
- rdev->mc.vram_location = 0xFFFFFFFFUL;
- rdev->mc.gtt_location = 0xFFFFFFFFUL;
- if (rdev->flags & RADEON_IS_AGP) {
- r = radeon_agp_init(rdev);
- if (r) {
- printk(KERN_WARNING "[drm] Disabling AGP\n");
- rdev->flags &= ~RADEON_IS_AGP;
- rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
- } else {
- rdev->mc.gtt_location = rdev->mc.agp_base;
- }
- }
- r = radeon_mc_setup(rdev);
- if (r) {
- return r;
- }
- return 0;
-}
-
void r420_pipes_init(struct radeon_device *rdev)
{
unsigned tmp;
@@ -314,7 +290,7 @@ int r420_init(struct radeon_device *rdev)
/* Get vram informations */
r300_vram_info(rdev);
/* Initialize memory controller (also test AGP) */
- r = r420_mc_init(rdev);
+ r = r100_mc_init(rdev);
if (r) {
return r;
}
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 0f3843b..0f534b2 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -144,8 +144,6 @@ void r520_mc_program(struct radeon_device *rdev)
/* Wait for mc idle */
if (r520_mc_wait_for_idle(rdev))
dev_warn(rdev->dev, "Wait MC idle timeout before updating
MC.\n");
- /* Write VRAM size in case we are limiting it */
- WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
/* Program MC, should be a 32bits limited address space */
WREG32_MC(R_000004_MC_FB_LOCATION,
S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
@@ -269,7 +267,7 @@ int r520_init(struct radeon_device *rdev)
/* Get vram informations */
r520_vram_info(rdev);
/* Initialize memory controller (also test AGP) */
- r = r420_mc_init(rdev);
+ r = r100_mc_init(rdev);
if (r)
return r;
rv515_debugfs(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 5e28467..9b31604 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -657,69 +657,20 @@ int r600_mc_init(struct radeon_device *rdev)
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
/* Setup GPU memory space */
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
- rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
-
- if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
- rdev->mc.mc_vram_size = rdev->mc.aper_size;
-
- if (rdev->mc.real_vram_size > rdev->mc.aper_size)
- rdev->mc.real_vram_size = rdev->mc.aper_size;
-
+ rdev->mc.vram_size = rdev->mc.mc_vram_size;
+ if (rdev->mc.vram_size > rdev->mc.aper_size)
+ rdev->mc.vram_size = rdev->mc.aper_size;
+ if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size)
+ rdev->mc.vram_size = radeon_vram_limit;
if (rdev->flags & RADEON_IS_AGP) {
r = radeon_agp_init(rdev);
if (r)
return r;
- /* gtt_size is setup by radeon_agp_init */
- rdev->mc.gtt_location = rdev->mc.agp_base;
- tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
- /* Try to put vram before or after AGP because we
- * we want SYSTEM_APERTURE to cover both VRAM and
- * AGP so that GPU can catch out of VRAM/AGP access
- */
- if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
- /* Enought place before */
- rdev->mc.vram_location = rdev->mc.gtt_location -
- rdev->mc.mc_vram_size;
- } else if (tmp > rdev->mc.mc_vram_size) {
- /* Enought place after */
- rdev->mc.vram_location = rdev->mc.gtt_location +
- rdev->mc.gtt_size;
- } else {
- /* Try to setup VRAM then AGP might not
- * not work on some card
- */
- rdev->mc.vram_location = 0x00000000UL;
- rdev->mc.gtt_location = rdev->mc.mc_vram_size;
- }
+ radeon_mc_init_vram_location(rdev, 0);
} else {
- rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
- rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
- 0xFFFF) << 24;
- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
- if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
- /* Enough place after vram */
- rdev->mc.gtt_location = tmp;
- } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
- /* Enough place before vram */
- rdev->mc.gtt_location = 0;
- } else {
- /* Not enough place after or before shrink
- * gart size
- */
- if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
- rdev->mc.gtt_location = 0;
- rdev->mc.gtt_size = rdev->mc.vram_location;
- } else {
- rdev->mc.gtt_location = tmp;
- rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
- }
- }
- rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+ radeon_mc_init_vram_location(rdev, 0);
+ radeon_mc_init_gtt_location(rdev);
}
- rdev->mc.vram_start = rdev->mc.vram_location;
- rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
- rdev->mc.gtt_start = rdev->mc.gtt_location;
- rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
/* FIXME: we should enforce default clock in case GPU is not in
* default setup
*/
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index baec009..d4c786f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -298,8 +298,21 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned
offset,
int pages, struct page **pagelist);
-/*
- * GPU MC structures, functions & helpers
+/**
+ * struct radeon_mc
+ *
+ * @aper_size: vram aperture size
+ * @aper_base: vram aperture base address in CPU address space
+ * @mc_vram_size: real vram size (can be > aperture size)
+ * @gtt_size: gtt size
+ * @gtt_start: gtt start address in GPU address space
+ * @gtt_end: gtt end address in GPU address space (start + size - 1)
+ * @vram_start: vram start address in GPU address space
+ * @vram_end: vram end address in GPU address space (start + size - 1)
+ * @vram_width: vram bus size in bits (64bits, 128bits, ...)
+ * @vram_size: vram reported size always <= mc_vram_size
+ * @vram_mtrr: mtrr entry covering vram aperture
+ * @vram_is_ddr: vram is ddr
*/
struct radeon_mc {
resource_size_t aper_size;
@@ -308,21 +321,17 @@ struct radeon_mc {
/* for some chips with <= 32MB we need to lie
* about vram size near mc fb location */
u64 mc_vram_size;
- u64 gtt_location;
u64 gtt_size;
u64 gtt_start;
u64 gtt_end;
- u64 vram_location;
u64 vram_start;
u64 vram_end;
unsigned vram_width;
- u64 real_vram_size;
+ u64 vram_size;
int vram_mtrr;
bool vram_is_ddr;
};
-int radeon_mc_setup(struct radeon_device *rdev);
-
/*
* GPU scratch registers structures, functions & helpers
@@ -1027,6 +1036,8 @@ extern int radeon_cs_parser_init(struct radeon_cs_parser
*p, void *data);
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int
enable);
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int
enable);
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32
domain);
+extern void radeon_mc_init_vram_location(struct radeon_device *rdev, u64 base);
+extern void radeon_mc_init_gtt_location(struct radeon_device *rdev);
/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
struct r100_mc_save {
@@ -1052,6 +1063,7 @@ extern void r100_ib_fini(struct radeon_device *rdev);
extern int r100_ib_init(struct radeon_device *rdev);
extern void r100_irq_disable(struct radeon_device *rdev);
extern int r100_irq_set(struct radeon_device *rdev);
+extern int r100_mc_init(struct radeon_device *rdev);
extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save
*save);
extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save
*save);
extern void r100_vram_init_sizes(struct radeon_device *rdev);
@@ -1090,7 +1102,6 @@ extern int rv370_pcie_gart_enable(struct radeon_device
*rdev);
extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
/* r420,r423,rv410 */
-extern int r420_mc_init(struct radeon_device *rdev);
extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c
b/drivers/gpu/drm/radeon/radeon_agp.c
index 54bf49a..466d3ab 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -226,6 +226,8 @@ int radeon_agp_init(struct radeon_device *rdev)
rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base;
rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20;
+ rdev->mc.gtt_start = rdev->mc.agp_base;
+ rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1;
/* workaround some hw issues */
if (rdev->family < CHIP_R200) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index ff5a955..22de145 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -100,80 +100,112 @@ void radeon_scratch_free(struct radeon_device *rdev,
uint32_t reg)
}
}
-/*
- * MC common functions
+
+/**
+ * radeon_mc_init_vram_location - initialize vram location
+ * @rdev: radeon device structure holding all necessary informations
+ * @base: base address for VRAM in GPU address space
+ *
+ * Function will place VRAM location so that it start at base
+ * address. Most of radeon hw won't work if it's not the case (hw
+ * starting with R6XX family should be fine). There is 2 corners case :
+ * - 32bits address space exhaustion ie : 0xFFFFFFFF - base < vram-size
+ * (including non visible) To work around this we limit vram size meaning
+ * we are not going to use the non visible vram. Hopefully this case
+ * shouldn't happen often. Other possible solution is to place vram else
+ * where than bar but in our experiences this lead to too much trouble.
+ * We might seek more help from AMD on this matter sadly hw is old and
+ * engineer forget about it.
+ * - base + vram size conflict with AGP aperture, only problematic with AGP
+ * device. Again we have never been able to get reliable working
+ * GPU by putting AGP space (in GPU address space) at different address
+ * that the one in the pci address space (once again buggy hw). Again we
+ * fallback to limiting VRAM size, hopefully this unlikely to happen.
+ * Note: GTT start, end, size should be initialized before calling this
+ * function on AGP platform.
*/
-int radeon_mc_setup(struct radeon_device *rdev)
+void radeon_mc_init_vram_location(struct radeon_device *rdev, u64 base)
{
- uint32_t tmp;
-
+ rdev->mc.vram_start = base;
/* Some chips have an "issue" with the memory controller, the
* location must be aligned to the size. We just align it down,
* too bad if we walk over the top of system memory, we don't
* use DMA without a remapped anyway.
* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
*/
- /* FGLRX seems to setup like this, VRAM a 0, then GART.
- */
- /*
- * Note: from R6xx the address space is 40bits but here we only
- * use 32bits (still have to see a card which would exhaust 4G
- * address space).
- */
- if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
- /* vram location was already setup try to put gtt after
- * if it fits */
- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
- tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
- if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
- rdev->mc.gtt_location = tmp;
- } else {
- if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
- printk(KERN_ERR "[drm] GTT too big to fit "
- "before or after vram location.\n");
- return -EINVAL;
- }
- rdev->mc.gtt_location = 0;
- }
- } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
- /* gtt location was already setup try to put vram before
- * if it fits */
- if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
- rdev->mc.vram_location = 0;
+ rdev->mc.vram_start &= ~(rdev->mc.mc_vram_size - 1);
+ if ((0xFFFFFFFFUL - rdev->mc.vram_start) < rdev->mc.mc_vram_size) {
+ dev_warn(rdev->dev, "0x%08llX - 0xFFFFFFFF too small for "
+ "0x%08llX limiting VRAM to 0x%08llX\n",
+ rdev->mc.vram_start, rdev->mc.mc_vram_size,
+ (u64)rdev->mc.aper_size);
+ rdev->mc.mc_vram_size = rdev->mc.aper_size;
+ }
+ rdev->mc.vram_end = rdev->mc.vram_start + rdev->mc.mc_vram_size - 1;
+ if ((rdev->flags & RADEON_IS_AGP) &&
+ rdev->mc.vram_end > rdev->mc.gtt_start &&
+ rdev->mc.vram_end < rdev->mc.gtt_end) {
+ dev_warn(rdev->dev, "0x%08llX - 0x%08llX conflict with AGP "
+ "aperture 0x%08llX-0x%08llX limiting VRAM to "
+ "0x%08llX\n", rdev->mc.vram_start,
+ rdev->mc.vram_end, rdev->mc.gtt_start,
+ rdev->mc.gtt_end, (u64)rdev->mc.aper_size);
+ rdev->mc.mc_vram_size = rdev->mc.aper_size;
+ }
+ rdev->mc.vram_end = rdev->mc.vram_start + rdev->mc.mc_vram_size - 1;
+ rdev->mc.vram_size = rdev->mc.mc_vram_size;
+ /* FIXME: Limit VRAM to aperture size for the moment */
+ if (rdev->mc.vram_size > rdev->mc.aper_size)
+ rdev->mc.vram_size = rdev->mc.aper_size;
+ if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size)
+ rdev->mc.vram_size = radeon_vram_limit;
+ dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
+ rdev->mc.mc_vram_size >> 20, rdev->mc.vram_start,
+ rdev->mc.vram_end, rdev->mc.vram_size >> 20);
+}
+
+/**
+ * radeon_mc_init_gtt_location - initialize gtt location
+ * @rdev: radeon device structure holding all necessary informations
+ *
+ * Function will place GTT location to be after VRAM if enough place
+ * or before VRAM. If there isn't enought neither before or after VRAM
+ * it will use the biggest possible power of two which fits either after
+ * or before VRAM and change GTT size to that. Don't call this function
+ * to place AGP aperture.
+ */
+void radeon_mc_init_gtt_location(struct radeon_device *rdev)
+{
+ u32 vram_end;
+
+ vram_end = rdev->mc.vram_start + rdev->mc.mc_vram_size;
+ if ((0xFFFFFFFFUL - vram_end) >= rdev->mc.gtt_size) {
+ rdev->mc.gtt_start = vram_end;
+ rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1;
+ } else if (rdev->mc.vram_start >= rdev->mc.gtt_size) {
+ rdev->mc.gtt_start = rdev->mc.gtt_start - rdev->mc.gtt_size;
+ rdev->mc.gtt_end = rdev->mc.vram_start - 1;
+ } else {
+ if (rdev->mc.vram_start > (0xFFFFFFFFUL - vram_end)) {
+ rdev->mc.gtt_size = rdev->mc.vram_start;
+ rounddown_pow_of_two(rdev->mc.gtt_size);
+ rdev->mc.gtt_start = rdev->mc.vram_start -
+ rdev->mc.gtt_size;
} else {
- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
- tmp += (rdev->mc.mc_vram_size - 1);
- tmp &= ~(rdev->mc.mc_vram_size - 1);
- if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
- rdev->mc.vram_location = tmp;
- } else {
- printk(KERN_ERR "[drm] vram too big to fit "
- "before or after GTT location.\n");
- return -EINVAL;
- }
+ rdev->mc.gtt_start = vram_end;
+ rdev->mc.gtt_size = 0xFFFFFFFFUL - vram_end;
+ rounddown_pow_of_two(rdev->mc.gtt_size);
}
- } else {
- rdev->mc.vram_location = 0;
- tmp = rdev->mc.mc_vram_size;
- tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
- rdev->mc.gtt_location = tmp;
- }
- rdev->mc.vram_start = rdev->mc.vram_location;
- rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
- rdev->mc.gtt_start = rdev->mc.gtt_location;
- rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
- DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
- DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
- (unsigned)rdev->mc.vram_location,
- (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size -
1));
- DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
- DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
- (unsigned)rdev->mc.gtt_location,
- (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
- return 0;
+ rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_end - 1;
+ dev_warn(rdev->dev, "Not enought place before or after VRAM "
+ "limiting GTT to 0x%08llX\n",
+ rdev->mc.gtt_size);
+ }
+ dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
+ rdev->mc.gtt_size >> 20, rdev->mc.gtt_start,
+ rdev->mc.gtt_end);
}
-
/*
* GPU helpers function.
*/
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c
b/drivers/gpu/drm/radeon/radeon_fb.c
index 66055b3..b78c897 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -257,7 +257,7 @@ int radeonfb_create(struct drm_device *dev,
info->flags = FBINFO_DEFAULT;
info->fbops = &radeonfb_ops;
- tmp = fb_gpuaddr - rdev->mc.vram_location;
+ tmp = fb_gpuaddr - rdev->mc.vram_start;
info->fix.smem_start = rdev->mc.aper_base + tmp;
info->fix.smem_len = size;
info->screen_base = fbptr;
@@ -267,7 +267,7 @@ int radeonfb_create(struct drm_device *dev,
/* setup aperture base/size for vesafb takeover */
info->aperture_base = rdev->ddev->mode_config.fb_base;
- info->aperture_size = rdev->mc.real_vram_size;
+ info->aperture_size = rdev->mc.vram_size;
info->fix.mmio_start = 0;
info->fix.mmio_len = 0;
@@ -335,7 +335,7 @@ int radeonfb_probe(struct drm_device *dev)
int bpp_sel = 32;
/* select 8 bpp console on RN50 or 16MB cards */
- if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
+ if (ASIC_IS_RN50(rdev) || rdev->mc.vram_size <= (32*1024*1024))
bpp_sel = 8;
return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeonfb_create);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
b/drivers/gpu/drm/radeon/radeon_gem.c
index e927f99..1ef4361 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -156,8 +156,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void
*data,
struct radeon_device *rdev = dev->dev_private;
struct drm_radeon_gem_info *args = data;
- args->vram_size = rdev->mc.real_vram_size;
- args->vram_visible = rdev->mc.real_vram_size;
+ args->vram_size = rdev->mc.vram_size;
+ args->vram_visible = rdev->mc.vram_size;
if (rdev->stollen_vga_memory)
args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory);
if (rdev->fbdev_rbo)
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index b82ede9..4ee39b1 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -467,7 +467,7 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int
y,
/* if scanout was in GTT this really wouldn't work */
/* crtc offset is from display base addr not FB location */
- radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
+ radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
base -= radeon_crtc->legacy_display_base_addr;
diff --git a/drivers/gpu/drm/radeon/radeon_test.c
b/drivers/gpu/drm/radeon/radeon_test.c
index 391c973..94ac64c 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -186,7 +186,7 @@ void radeon_test_moves(struct radeon_device *rdev)
radeon_bo_kunmap(gtt_obj[i]);
DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset
0x%llx\n",
- gtt_addr - rdev->mc.gtt_location);
+ gtt_addr - rdev->mc.gtt_start);
}
out_cleanup:
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 310562a..74a6a9f 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -150,7 +150,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
man->default_caching = TTM_PL_FLAG_CACHED;
break;
case TTM_PL_TT:
- man->gpu_offset = rdev->mc.gtt_location;
+ man->gpu_offset = rdev->mc.gtt_start;
man->available_caching = TTM_PL_MASK_CACHING;
man->default_caching = TTM_PL_FLAG_CACHED;
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -180,7 +180,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
break;
case TTM_PL_VRAM:
/* "On-card" video ram */
- man->gpu_offset = rdev->mc.vram_location;
+ man->gpu_offset = rdev->mc.vram_start;
man->flags = TTM_MEMTYPE_FLAG_FIXED |
TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
TTM_MEMTYPE_FLAG_MAPPABLE;
@@ -247,10 +247,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
switch (old_mem->mem_type) {
case TTM_PL_VRAM:
- old_start += rdev->mc.vram_location;
+ old_start += rdev->mc.vram_start;
break;
case TTM_PL_TT:
- old_start += rdev->mc.gtt_location;
+ old_start += rdev->mc.gtt_start;
break;
default:
DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
@@ -258,10 +258,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
}
switch (new_mem->mem_type) {
case TTM_PL_VRAM:
- new_start += rdev->mc.vram_location;
+ new_start += rdev->mc.vram_start;
break;
case TTM_PL_TT:
- new_start += rdev->mc.gtt_location;
+ new_start += rdev->mc.gtt_start;
break;
default:
DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
@@ -484,7 +484,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
}
rdev->mman.initialized = true;
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
- rdev->mc.real_vram_size >> PAGE_SHIFT);
+ rdev->mc.vram_size >> PAGE_SHIFT);
if (r) {
DRM_ERROR("Failed initializing VRAM heap.\n");
return r;
@@ -504,20 +504,15 @@ int radeon_ttm_init(struct radeon_device *rdev)
radeon_bo_unref(&rdev->stollen_vga_memory);
return r;
}
- DRM_INFO("radeon: %uM of VRAM memory ready\n",
- (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
rdev->mc.gtt_size >> PAGE_SHIFT);
if (r) {
DRM_ERROR("Failed initializing GTT heap.\n");
return r;
}
- DRM_INFO("radeon: %uM of GTT memory ready.\n",
- (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
}
-
r = radeon_ttm_debugfs_init(rdev);
if (r) {
DRM_ERROR("Failed to init debugfs\n");
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index c1fcddd..c0819ac 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -150,9 +150,8 @@ int rs400_gart_enable(struct radeon_device *rdev)
WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
WREG32(RS480_AGP_BASE_2, 0);
}
- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
- tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
- tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
+ tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
+ tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
@@ -348,16 +347,13 @@ static int rs400_debugfs_pcie_gart_info_init(struct
radeon_device *rdev)
static int rs400_mc_init(struct radeon_device *rdev)
{
- int r;
u32 tmp;
- /* Setup GPU memory space */
+ /* read back the MC value from the hw */
tmp = RREG32(R_00015C_NB_TOM);
- rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
- rdev->mc.gtt_location = 0xFFFFFFFFUL;
- r = radeon_mc_setup(rdev);
- if (r)
- return r;
+ rdev->mc.vram_start = G_00015C_MC_FB_START(tmp) << 16;
+ rdev->mc.vram_end = (G_00015C_MC_FB_TOP(tmp) << 16) | 0xFFFF;
+ radeon_mc_init_gtt_location(rdev);
return 0;
}
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 4f8ea42..f61e47f 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -47,17 +47,13 @@ int rs600_mc_wait_for_idle(struct radeon_device *rdev);
int rs600_mc_init(struct radeon_device *rdev)
{
- /* read back the MC value from the hw */
- int r;
u32 tmp;
- /* Setup GPU memory space */
+ /* read back the MC value from the hw */
tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
- rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
- rdev->mc.gtt_location = 0xffffffffUL;
- r = radeon_mc_setup(rdev);
- if (r)
- return r;
+ rdev->mc.vram_start = G_000004_MC_FB_START(tmp) << 16;
+ rdev->mc.vram_end = (G_000004_MC_FB_TOP(tmp) << 16) | 0xFFFF;
+ radeon_mc_init_gtt_location(rdev);
return 0;
}
@@ -468,17 +464,14 @@ void rs600_vram_info(struct radeon_device *rdev)
rdev->mc.vram_is_ddr = true;
rdev->mc.vram_width = 128;
- rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
- rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
-
+ rdev->mc.mc_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
-
- if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
- rdev->mc.mc_vram_size = rdev->mc.aper_size;
-
- if (rdev->mc.real_vram_size > rdev->mc.aper_size)
- rdev->mc.real_vram_size = rdev->mc.aper_size;
+ rdev->mc.vram_size = rdev->mc.mc_vram_size;
+ if (rdev->mc.vram_size > rdev->mc.aper_size)
+ rdev->mc.vram_size = rdev->mc.aper_size;
+ if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size)
+ rdev->mc.vram_size = radeon_vram_limit;
}
void rs600_bandwidth_update(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 1e22f52..e058660 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -138,17 +138,14 @@ void rs690_vram_info(struct radeon_device *rdev)
rdev->mc.vram_is_ddr = true;
rdev->mc.vram_width = 128;
- rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
- rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
-
+ rdev->mc.mc_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
-
- if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
- rdev->mc.mc_vram_size = rdev->mc.aper_size;
-
- if (rdev->mc.real_vram_size > rdev->mc.aper_size)
- rdev->mc.real_vram_size = rdev->mc.aper_size;
+ rdev->mc.vram_size = rdev->mc.mc_vram_size;
+ if (rdev->mc.vram_size > rdev->mc.aper_size)
+ rdev->mc.vram_size = rdev->mc.aper_size;
+ if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size)
+ rdev->mc.vram_size = radeon_vram_limit;
rs690_pm_info(rdev);
/* FIXME: we should enforce default clock in case GPU is not in
@@ -164,16 +161,13 @@ void rs690_vram_info(struct radeon_device *rdev)
static int rs690_mc_init(struct radeon_device *rdev)
{
- int r;
u32 tmp;
- /* Setup GPU memory space */
+ /* read back the MC value from the hw */
tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
- rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
- rdev->mc.gtt_location = 0xFFFFFFFFUL;
- r = radeon_mc_setup(rdev);
- if (r)
- return r;
+ rdev->mc.vram_start = G_000100_MC_FB_START(tmp) << 16;
+ rdev->mc.vram_end = (G_000100_MC_FB_TOP(tmp) << 16) | 0xFFFF;
+ radeon_mc_init_gtt_location(rdev);
return 0;
}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 59632a5..fcf6305 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -424,8 +424,6 @@ void rv515_mc_program(struct radeon_device *rdev)
/* Wait for mc idle */
if (rv515_mc_wait_for_idle(rdev))
dev_warn(rdev->dev, "Wait MC idle timeout before updating
MC.\n");
- /* Write VRAM size in case we are limiting it */
- WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
/* Program MC, should be a 32bits limited address space */
WREG32_MC(R_000001_MC_FB_LOCATION,
S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
@@ -590,7 +588,7 @@ int rv515_init(struct radeon_device *rdev)
/* Get vram informations */
rv515_vram_info(rdev);
/* Initialize memory controller (also test AGP) */
- r = r420_mc_init(rdev);
+ r = r100_mc_init(rdev);
if (r)
return r;
rv515_debugfs(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 2d124bb..3279921 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -813,49 +813,20 @@ int rv770_mc_init(struct radeon_device *rdev)
rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
/* Setup GPU memory space */
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
- rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
-
- if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
- rdev->mc.mc_vram_size = rdev->mc.aper_size;
-
- if (rdev->mc.real_vram_size > rdev->mc.aper_size)
- rdev->mc.real_vram_size = rdev->mc.aper_size;
-
+ rdev->mc.vram_size = rdev->mc.mc_vram_size;
+ if (rdev->mc.vram_size > rdev->mc.aper_size)
+ rdev->mc.vram_size = rdev->mc.aper_size;
+ if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size)
+ rdev->mc.vram_size = radeon_vram_limit;
if (rdev->flags & RADEON_IS_AGP) {
r = radeon_agp_init(rdev);
if (r)
return r;
- /* gtt_size is setup by radeon_agp_init */
- rdev->mc.gtt_location = rdev->mc.agp_base;
- tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
- /* Try to put vram before or after AGP because we
- * we want SYSTEM_APERTURE to cover both VRAM and
- * AGP so that GPU can catch out of VRAM/AGP access
- */
- if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
- /* Enought place before */
- rdev->mc.vram_location = rdev->mc.gtt_location -
- rdev->mc.mc_vram_size;
- } else if (tmp > rdev->mc.mc_vram_size) {
- /* Enought place after */
- rdev->mc.vram_location = rdev->mc.gtt_location +
- rdev->mc.gtt_size;
- } else {
- /* Try to setup VRAM then AGP might not
- * not work on some card
- */
- rdev->mc.vram_location = 0x00000000UL;
- rdev->mc.gtt_location = rdev->mc.mc_vram_size;
- }
+ radeon_mc_init_vram_location(rdev, 0);
} else {
- rdev->mc.vram_location = 0x00000000UL;
- rdev->mc.gtt_location = rdev->mc.mc_vram_size;
- rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+ radeon_mc_init_vram_location(rdev, 0);
+ radeon_mc_init_gtt_location(rdev);
}
- rdev->mc.vram_start = rdev->mc.vram_location;
- rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
- rdev->mc.gtt_start = rdev->mc.gtt_location;
- rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
/* FIXME: we should enforce default clock in case GPU is not in
* default setup
*/
--
1.6.5.2
------------------------------------------------------------------------------
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