Rename the CamelCase. Use the BIT() marco to define the bits.
Signed-off-by: H Hartley Sweeten <hswee...@visionengravers.com>
Cc: Ian Abbott <abbo...@mev.co.uk>
Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org>
---
drivers/staging/comedi/drivers/ni_mio_common.c | 29 +++++++++++-----------
drivers/staging/comedi/drivers/ni_stc.h | 33 +++++++++++++-------------
2 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c
b/drivers/staging/comedi/drivers/ni_mio_common.c
index 187a261..c0bd097 100644
--- a/drivers/staging/comedi/drivers/ni_mio_common.c
+++ b/drivers/staging/comedi/drivers/ni_mio_common.c
@@ -379,7 +379,7 @@ static const struct mio_regmap m_series_stc_write_regmap[]
= {
[NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
[NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
[NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
- [AI_Mode_3_Register] = { 0x1ae, 2 },
+ [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
};
static void m_series_stc_write(struct comedi_device *dev,
@@ -1630,7 +1630,8 @@ static int ni_ai_reset(struct comedi_device *dev, struct
comedi_subdevice *s)
NISTC_AI_MODE1_REG);
ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
/* generate FIFO interrupts on non-empty */
- ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
+ ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
+ NISTC_AI_MODE3_REG);
ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
NISTC_AI_PERSONAL_SOC_POLARITY |
@@ -1657,7 +1658,7 @@ static int ni_ai_reset(struct comedi_device *dev, struct
comedi_subdevice *s)
* are no backup registers in devpriv. If you want to change
* any of these, add a backup register and other appropriate code:
* NISTC_AI_MODE1_REG
- * AI_Mode_3_Register
+ * NISTC_AI_MODE3_REG
* NISTC_AI_PERSONAL_REG
* NISTC_AI_OUT_CTRL_REG
*/
@@ -2335,7 +2336,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct
comedi_subdevice *s)
case TRIG_TIMER:
/*
* stop bits for non 611x boards
- * AI_SI_Special_Trigger_Delay=0
+ * NISTC_AI_MODE3_SI_TRIG_DELAY=0
* NISTC_AI_MODE2_PRE_TRIGGER=0
* NISTC_AI_START_STOP_REG:
* NISTC_AI_START_POLARITY=0 (?) rising edge
@@ -2432,25 +2433,25 @@ static int ni_ai_cmd(struct comedi_device *dev, struct
comedi_subdevice *s)
case AIMODE_HALF_FULL:
/*generate FIFO interrupts and DMA requests on
half-full */
#ifdef PCIDMA
- ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E,
- AI_Mode_3_Register);
+ ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
+ NISTC_AI_MODE3_REG);
#else
- ni_stc_writew(dev, AI_FIFO_Mode_HF,
- AI_Mode_3_Register);
+ ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
+ NISTC_AI_MODE3_REG);
#endif
break;
case AIMODE_SAMPLE:
/*generate FIFO interrupts on non-empty */
- ni_stc_writew(dev, AI_FIFO_Mode_NE,
- AI_Mode_3_Register);
+ ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
+ NISTC_AI_MODE3_REG);
break;
case AIMODE_SCAN:
#ifdef PCIDMA
- ni_stc_writew(dev, AI_FIFO_Mode_NE,
- AI_Mode_3_Register);
+ ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
+ NISTC_AI_MODE3_REG);
#else
- ni_stc_writew(dev, AI_FIFO_Mode_HF,
- AI_Mode_3_Register);
+ ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
+ NISTC_AI_MODE3_REG);
#endif
interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
break;
diff --git a/drivers/staging/comedi/drivers/ni_stc.h
b/drivers/staging/comedi/drivers/ni_stc.h
index 230744f..6c9bb6c 100644
--- a/drivers/staging/comedi/drivers/ni_stc.h
+++ b/drivers/staging/comedi/drivers/ni_stc.h
@@ -475,6 +475,23 @@
#define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2)
#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3)
+#define NISTC_AI_MODE3_REG 87
+#define NISTC_AI_MODE3_TRIG_LEN BIT(15)
+#define NISTC_AI_MODE3_DELAY_START BIT(14)
+#define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13)
+#define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12)
+#define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11)
+#define NISTC_AI_MODE3_DELAYED_START2 BIT(10)
+#define NISTC_AI_MODE3_DELAYED_START1 BIT(9)
+#define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8)
+#define NISTC_AI_MODE3_FIFO_MODE(x) (((x) & 0x3) << 6)
+#define NISTC_AI_MODE3_FIFO_MODE_NE NISTC_AI_MODE3_FIFO_MODE(0)
+#define NISTC_AI_MODE3_FIFO_MODE_HF NISTC_AI_MODE3_FIFO_MODE(1)
+#define NISTC_AI_MODE3_FIFO_MODE_F NISTC_AI_MODE3_FIFO_MODE(2)
+#define NISTC_AI_MODE3_FIFO_MODE_HF_E NISTC_AI_MODE3_FIFO_MODE(3)
+#define NISTC_AI_MODE3_EXT_GATE_POL BIT(5)
+#define NISTC_AI_MODE3_EXT_GATE_SEL(x) (((x) & 0x1f) << 0)
+
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
@@ -533,22 +550,6 @@ enum Joint_Status_2_Bits {
#define AO_BC_Save_Registers 18
#define AO_UC_Save_Registers 20
-#define AI_Mode_3_Register 87
-#define AI_Trigger_Length _bit15
-#define AI_Delay_START _bit14
-#define AI_Software_Gate _bit13
-#define AI_SI_Special_Trigger_Delay _bit12
-#define AI_SI2_Source_Select _bit11
-#define AI_Delayed_START2 _bit10
-#define AI_Delayed_START1 _bit9
-#define AI_External_Gate_Mode _bit8
-#define AI_FIFO_Mode_HF_to_E (3<<6)
-#define AI_FIFO_Mode_F (2<<6)
-#define AI_FIFO_Mode_HF (1<<6)
-#define AI_FIFO_Mode_NE (0<<6)
-#define AI_External_Gate_Polarity _bit5
-#define AI_External_Gate_Select(a) ((a) & 0x1f)
-
#define G_HW_Save_Register(a) (8+(a)*2)
#define G_HW_Save_Register_High(a) (8+(a)*2)
#define G_HW_Save_Register_Low(a) (9+(a)*2)
--
2.3.0
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