The order of the internal clocks does not match how the hardware
is arranged. We need to fix this before we can add new function.
Swap the order of the internal multiplier and divider clocks so that the
divider is the parent of the multiplier.
Signed-off-by: James Kelly <jamespeterke...@gmail.com>
---
.../clocking-wizard/clk-xlnx-clock-wizard.c | 37 +++++++++++-----------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
index babbed42f96d..1d42eabdd956 100644
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
@@ -84,8 +84,8 @@
#define WZRD_CLKOUT_DIVIDE_MASK (0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
enum clk_wzrd_int_clks {
- wzrd_clk_mul,
wzrd_clk_mul_div,
+ wzrd_clk_mul,
wzrd_clk_int_max
};
@@ -243,41 +243,40 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (reg)
dev_warn(&pdev->dev, "fractional div/mul not supported\n");
- /* register multiplier */
+ /* register div */
reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_CLKFBOUT_MULT_MASK) >> WZRD_CLKFBOUT_MULT_SHIFT;
- clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
+ WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
+ clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
if (!clk_name) {
ret = -ENOMEM;
goto err_disable_clk;
}
- clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor(
+ clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor(
&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clk_in1),
- 0, reg, 1);
+ 0, 1, reg);
kfree(clk_name);
- if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
- dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
- ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
+ if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
+ dev_err(&pdev->dev, "unable to register divider clock\n");
+ ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
goto err_disable_clk;
}
- /* register div */
+ /* register multiplier */
reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
- clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
+ WZRD_CLKFBOUT_MULT_MASK) >> WZRD_CLKFBOUT_MULT_SHIFT;
+ clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
if (!clk_name) {
ret = -ENOMEM;
goto err_rm_int_clk;
}
-
- clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor(
+ clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor(
&pdev->dev, clk_name,
- __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
- 0, 1, reg);
- if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
- dev_err(&pdev->dev, "unable to register divider clock\n");
- ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
+
__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul_div]),
+ 0, reg, 1);
+ if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
+ dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
+ ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
goto err_rm_int_clk;
}
--
2.15.1 (Apple Git-101)
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