On 7.5.2018 03:20, James Kelly wrote:
> Add support for the clk_round_rate API to our CCF clock provider.
>
> Signed-off-by: James Kelly <jamespeterke...@gmail.com>
> ---
> .../clocking-wizard/clk-xlnx-clock-wizard.c | 107
> +++++++++++++++++++++
> 1 file changed, 107 insertions(+)
>
> diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
> b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
> index 8929913045e7..8828dac6faaf 100644
> --- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
> +++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
> @@ -83,6 +83,7 @@
> #define WZRD_CLKNAME_IN1 "clk_in1"
> #define WZRD_FLAG_MULTIPLY BIT(0)
> #define WZRD_FLAG_FRAC BIT(1)
> +#define WZRD_FLAG_ADJUST_MIN BIT(2)
>
> /*
> * Clock rate constraints extracted from Xilinx data sheets listed below.
> @@ -309,16 +310,19 @@ static const struct reg_field clk_wzrd_reconfig =
> REG_FIELD(0x25C, 0, 1);
> *
> * @hw: handle between common and hardware-specific
> interfaces
> * @flags: hardware specific flags
> + * @ratio_limit: pointer to divider/multiplier ratio limits
> * @int_field: pointer to regmap field for integer part
> * @frac_field: pointer to regmap field for fractional part
> *
> * Flags:
> * WZRD_FLAG_MULTIPLY Clock is a multiplier rather than a divider
> * WZRD_FLAG_FRAC Clock ratio can be fractional
> + * WZRD_FLAG_ADJUST_MIN When clock is fractional minimum ratio
> increases by 1
If you look at this as man page
./scripts/kernel-doc -man -v
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | nroff -man | less
Then you will get:
Description
Flags: WZRD_FLAG_MULTIPLY Clock is a multiplier rather than a
divider
WZRD_FLAG_FRAC Clock ratio can be fractional
WZRD_FLAG_ADJUST_MIN
When clock is fractional minimum ratio increases by 1
Which doesn't look nice.
Thanks,
Michal
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