Thank you John,
> Is the interrupt shared with other devices? Do things work
> correctly with a newer kernel? What kind of system is this?
Yes, the interrupts are shared with each devices.
IOAPIC and MSI are disabled by kernel options.
I have used only 2.6.10 and not tried the newer kernel yet.
Here is the output of /proc/interrupts.
dsppci* are the devices we developed.
CPU0
0: 4156373 XT-PIC timer 0/56373
1: 8 XT-PIC i8042 0/8
2: 0 XT-PIC cascade 0/0
4: 7 XT-PIC serial 0/7
5: 65122 XT-PIC HDA Intel, uhci_hcd, dsppci0 0/65122
7: 552750 XT-PIC ehci_hcd, uhci_hcd 0/52750
9: 0 XT-PIC acpi 0/0
10: 64995 XT-PIC dsppci1 0/64995
11: 192084 XT-PIC uhci_hcd, eth0, dsppci2 0/92084
14: 58499 XT-PIC ide0 0/58499
15: 794424 XT-PIC libata, uhci_hcd, dsppci3 0/94424
NMI: 0
ERR: 0
This system is the pc-based network equipment.
CPU is Celeron-D and the chipset is 945G+ICH7R.
There are another 4-pci boards we developed. (dsppci* above)
If you need other information, please let me know.
And please also refer my reply to Jesse.
Thanks,
Hizume
> -----Original Message-----
> From: Ronciak, John [mailto:[email protected]]
> Sent: Wednesday, July 01, 2009 11:23 PM
> To: Yosuke HIZUME; [email protected]
> Subject: RE: [E1000-devel] e1000e: Rx Descriptor FIFO Parity Error
>
> Is the interrupt shared with other devices? Do things work
> correctly with a newer kernel? What kind of system is this?
>
> Cheers,
> John
> -----------------------------------------------------------
> "...that your people will judge you on what you can build,
> not what you destroy.", B. Obama, 2009
>
>
>
> >-----Original Message-----
> >From: Yosuke HIZUME [mailto:[email protected]]
> >Sent: Wednesday, July 01, 2009 2:30 AM
> >To: [email protected]
> >Subject: [E1000-devel] e1000e: Rx Descriptor FIFO Parity Error
> >
> >Dear experts,
> >
> >I'm using e1000e-0.5.8.13 *Non-NAPI* on kernel 2.6.10 with 82573L.
> >I found the receiving data was occasionally corrupted just after I
> >changed the mtu or the speed and duplex setting.
> >
> >Then I inserted some printk codes to investigate and found that
> >e1000_intr() was infrequently called sometime in between the
> >beginning of
> >e1000e_down() and the end of e1000e_up() despite the irq was
> disabled.
> >
> >In such case, the register ICR.INT_ASSERTED was not set and
> >ICR.RX_DESC_FIFO_Par0 was set. (ex. icr=0x00100000h)
> >
> >I want to know the reason why the interrupt handler was called
> >nevertheless interrupt disabled, and also the reason why
> >RX_DESC_FIFO_Par0 was set.
> >And hopefully, please let me know if there are any workarounds.
> >
> >Best regards,
> >Hizume
> >
> >
> >---------------------------------------------------------------
> >---------------
> >_______________________________________________
> >E1000-devel mailing list
> >[email protected]
> >https://lists.sourceforge.net/lists/listinfo/e1000-devel
> >
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