There is no need to issue a full data synchronization barrier and an instruction synchronization barrier after each and every set/way or MVA cache maintenance operation. For the set/way case, we can simply remove them, since the set/way outer loop already issues the required barriers after completing its traversal over all the cache levels.
For the MVA case, move the data synchronization barrier out of the loop, and add the instruction synchronization barrier to the I-cache invalidation by MVA routine. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> Reviewed-by: Mark Rutland <mark.rutl...@arm.com> --- ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c | 1 + ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 12 ------------ ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 12 ------------ ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 12 ------------ 4 files changed, 1 insertion(+), 36 deletions(-) diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index d8e53df6096e..d4c16a607465 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -35,6 +35,7 @@ CacheRangeOperation ( LineOperation(AlignedAddress); AlignedAddress += ArmCacheLineLength; } + ArmDataSynchronizationBarrier (); } VOID diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index f973a35c21d6..df2dc935c122 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -65,43 +65,31 @@ GCC_ASM_EXPORT (ArmReadCurrentEL) ASM_PFX(ArmInvalidateDataCacheEntryByMVA): dc ivac, x0 // Invalidate single data cache line - dsb sy - isb ret ASM_PFX(ArmCleanDataCacheEntryByMVA): dc cvac, x0 // Clean single data cache line - dsb sy - isb ret ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): dc civac, x0 // Clean and invalidate single data cache line - dsb sy - isb ret ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): dc isw, x0 // Invalidate this line - dsb sy - isb ret ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): dc cisw, x0 // Clean and Invalidate this line - dsb sy - isb ret ASM_PFX(ArmCleanDataCacheEntryBySetWay): dc csw, x0 // Clean this line - dsb sy - isb ret diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index fdc4d03776c8..93164b8f0ea4 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -62,42 +62,30 @@ GCC_ASM_EXPORT (ArmReadIdPfr1) ASM_PFX(ArmInvalidateDataCacheEntryByMVA): mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line - dsb - isb bx lr ASM_PFX(ArmCleanDataCacheEntryByMVA): mcr p15, 0, r0, c7, c10, 1 @clean single data cache line - dsb - isb bx lr ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line - dsb - isb bx lr ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line - dsb - isb bx lr ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line - dsb - isb bx lr ASM_PFX(ArmCleanDataCacheEntryBySetWay): mcr p15, 0, r0, c7, c10, 2 @ Clean this line - dsb - isb bx lr ASM_PFX(ArmInvalidateInstructionCache): diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index f16dd4a4ab01..d6f249038a05 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -62,42 +62,30 @@ CTRL_I_BIT EQU (1 << 12) ArmInvalidateDataCacheEntryByMVA mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line - dsb - isb bx lr ArmCleanDataCacheEntryByMVA mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line - dsb - isb bx lr ArmCleanInvalidateDataCacheEntryByMVA mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line - dsb - isb bx lr ArmInvalidateDataCacheEntryBySetWay mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line - dsb - isb bx lr ArmCleanInvalidateDataCacheEntryBySetWay mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line - dsb - isb bx lr ArmCleanDataCacheEntryBySetWay mcr p15, 0, r0, c7, c10, 2 ; Clean this line - dsb - isb bx lr -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel