On Fri, Nov 06, 2015 at 03:03:58PM +0100, Ard Biesheuvel wrote: > When allocating memory to perform non-coherent DMA, use the cache > writeback granularity rather than the data cache linesize for > alignment. This prevents the explicit cache management from corrupting > unrelated adjacent data if the cache writeback granularity exceeds > the cache linesize. > > Reported-by: Mark Rutland <mark.rutl...@arm.com> > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> > --- > ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c > b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c > index 12b194046ae7..7e352e665a30 100755 > --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c > +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c > @@ -277,7 +277,7 @@ ArmDmaLibConstructor ( > Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID > **)&gCpu); > ASSERT_EFI_ERROR(Status); > > - gCacheAlignment = ArmDataCacheLineLength (); > + gCacheAlignment = ArmCacheWritebackGranularity ();
I assume that per my comment on the previous patch, the function name might change here. Regardless, this makes the logic look correct to me: Reviewed-by: Mark Rutland <mark.rutl...@arm.com> Thanks, Mark. _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
