The need for a v2 legacy override to drive a GICv3 in v2 mode is no
longer necessary, now that the code that enabled the GIC distributor no
longer inadvertently kicks a v2 capable GICv3 into v2 mode. So remove
the PCD and all references to it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
ArmPkg/ArmPkg.dec | 3 --
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 1 -
ArmPkg/Drivers/ArmGic/ArmGicLib.c | 6 ++--
ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 3 --
ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf | 3 --
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 35 ++++----------------
6 files changed, 9 insertions(+), 42 deletions(-)
diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index ff4531e44106..e8021d20bc78 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -70,9 +70,6 @@ [PcdsFeatureFlag.common]
# Linux (instead of PSCI)
gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
- # Define if the GICv3 controller should use the GICv2 legacy
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
-
[PcdsFeatureFlag.ARM]
# Whether to map normal memory as non-shareable. FALSE is the safe choice,
but
# TRUE may be appropriate to fix performance problems if you don't care about
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
index e554301c4b28..31d90a6d473d 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
@@ -54,7 +54,6 @@ [Pcd.common]
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
[Depex]
gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 248e896c4b94..f218a8d7ef06 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -183,7 +183,7 @@ ArmGicEnableInterrupt (
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
- if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet
(PcdArmGicV3WithV2Legacy)) {
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
// Write set-enable register
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 <<
RegShift);
} else {
@@ -216,7 +216,7 @@ ArmGicDisableInterrupt (
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
- if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet
(PcdArmGicV3WithV2Legacy)) {
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
// Write clear-enable register
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 <<
RegShift);
} else {
@@ -249,7 +249,7 @@ ArmGicIsInterruptEnabled (
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
- if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet
(PcdArmGicV3WithV2Legacy)) {
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 *
RegOffset)) & (1 << RegShift)) != 0);
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase
(GicRedistributorBase, Revision);
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
index 047adac85ff4..62f20eb55294 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -46,6 +46,3 @@ [Packages]
[Pcd]
gArmPlatformTokenSpaceGuid.PcdCoreCount
-
-[FeaturePcd]
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
index fc2e1bc01efe..efea9c828170 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
@@ -47,6 +47,3 @@ [LibraryClasses]
[Pcd]
gArmPlatformTokenSpaceGuid.PcdCoreCount
-
-[FeaturePcd]
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index 4afa3d5a09c2..0a75850200bd 100644
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -254,9 +254,7 @@ GicV3DxeInitialize (
// We will be driving this GIC in native v3 mode, i.e., with Affinity
// Routing enabled. So ensure that the ARE bit is set.
//
- if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
- MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
- }
+ MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
@@ -274,33 +272,12 @@ GicV3DxeInitialize (
//
// Targets the interrupts to the Primary Cpu
//
+ MpId = ArmReadMpidr ();
+ CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 |
ARM_CORE_AFF3);
- if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by
reading
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are
banked to each
- // connected CPU. These 8 registers hold the CPU targets fields for
interrupts 0-31.
- // More Info in the GIC Specification about "Interrupt Processor Targets
Registers"
- //
- // Read the first Interrupt Processor Targets Register (that corresponds
to the 4
- // first SGIs)
- CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
-
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.
This value
- // is 0 when we run on a uniprocessor platform.
- if (CpuTarget != 0) {
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),
CpuTarget);
- }
- }
- } else {
- MpId = ArmReadMpidr ();
- CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 |
ARM_CORE_AFF3);
-
- // Route the SPIs to the primary CPU. SPIs start at the INTID 32
- for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
- MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
CpuTarget | ARM_GICD_IROUTER_IRM);
- }
+ // Route the SPIs to the primary CPU. SPIs start at the INTID 32
+ for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
+ MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
CpuTarget | ARM_GICD_IROUTER_IRM);
}
// Set binary point reg to 0x7 (no preemption)
--
1.9.1
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