On Thu, Dec 03, 2015 at 02:58:36PM +0100, Ard Biesheuvel wrote:
> In the function ArmGicEnableDistributor (), the Affinity Routing Enable
> (ARE) bit, which essentially defines whether the GIC runs in v2 or v3
> mode, is inadvertently cleared when enabling the GIC distributor if it
> is running in v3 mode. So fix that.
>
> Reported-by: Supreeth Venkatesh <supreeth.venkat...@arm.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> ---
> ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
> b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
> index 31572438d9a1..f90391b716b5 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c
> @@ -33,9 +33,9 @@ ArmGicEnableDistributor (
> MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
> } else {
> if (MmioRead32 (GicDistributorBase + ARM_GIC_ICDDCR) &
> ARM_GIC_ICDDCR_ARE) {
> - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x2);
> + MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x2);
Hilariously, the name of this register in the GIC architecture
reference manual isn't GIC_ICDDCR, but GICD_CTLR.
> } else {
> - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
> + MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
> }
> }
> }
> --
> 1.9.1
So, this is a bugfix, and you shouldn't have to fix the world for it,
but I dislike the magic hex values. Maybe time to make a note to go
back and clean this stuff up later on.
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
/
Leif
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