BTW, there is actually a bug with ATU configuration which will cause IO access
failure, and we need to apply an additional patch (this patch is generated after
PCI host bridge patch series) as attached to fix this.
Regards,
Heyi
On Tue, Apr 17, 2018 at 09:20:44AM +0800, Guo Heyi wrote:
> Hi Ard,
>
> I tested mm -io on D05, for root bridge 4 with CPU IO address starting from
> 0x8_abff0000, and it worked; both mm -io 0x8abff0000 and mm 0x8abff0000
> provided
> the same output. It seems there is no other limit for 64bit IO address after
> you
> fixed the issue in EFI shell mm command.
>
> Thanks and regards,
>
> Heyi
>
> On Mon, Apr 16, 2018 at 09:57:09PM +0800, Guo Heyi wrote:
> > Thanks, I will test mm command and let you know the result.
> >
> > Regards,
> >
> > Heyi
> >
> > On Fri, Apr 13, 2018 at 09:19:53AM +0200, Ard Biesheuvel wrote:
> > > On 13 April 2018 at 04:05, Guo Heyi <heyi....@linaro.org> wrote:
> > > > Hi Ard,
> > > >
> > > > Any comments?
> > > >
> > >
> > > Apologies for the delay. I have been travelling and am behind on email.
> > >
> > > > Anyway we can modify the code if you insist on using an intermediate
> > > > CPU IO
> > > > address space.
> > > >
> > >
> > > I have not made up my mind yet, to be honest. I agree there is a
> > > certain elegance to merging both translations, but I am concerned that
> > > existing EDK2 code may deal poorly with I/O addresses that require
> > > more than 32 bits to express.
> > >
> > > Did you try the mm command in the shell for instance? As you know, I
> > > recently removed an artificial address range limit there, but I wonder
> > > if it uses 64-bit variables for I/O ports.
>From guoh...@huawei.com Tue Apr 17 09:40:07 2018
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From: Heyi Guo <guoh...@huawei.com>
To: <heyi....@linaro.org>
CC: <phoenix.l...@huawei.com>, <mengfanr...@huawei.com>,
<zhangjinso...@huawei.com>
Subject: [PATCH] Hisilicon/Hi161x/PcieInit: fix address overlap
Date: Tue, 17 Apr 2018 09:35:22 +0800
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From: Heyi Guo <heyi....@linaro.org>
PCIe IO address ranges are overlapped by configuration address spaces
when we set CFG0/CFG1 address range starting from ECAM. It causes
access to IO space is routed to configuration space and returned with
wrong results.
So we limit address space for configuration type 0
starting from BusBase and type 1 from (BusBase + 2), to eliminate the
address range overlapping.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi....@linaro.org>
---
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c
index f2365b5..9a92fea 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c
@@ -96,11 +96,12 @@ SetAtuConfig0RW (
{
UINTN RbPciBase = Private->RbPciBar;
UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+ UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0);
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32));
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
@@ -124,12 +125,13 @@ SetAtuConfig1RW (
{
UINTN RbPciBase = Private->RbPciBar;
UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+ UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32));
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
--
2.8.1
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