On 04/09/13 00:38, Duane Voth wrote:
> So gdb => qemu: I can single step and get/set cpu regs, but I can't set
> breakpoints or step over subroutines... does qemu 1.2 support
> breakpoints? (anything to make this easier!)
You need the debug symbols for the qemu binary. Your distro may provide
them in a separate package, or not at all. In the latter case you should
rebuild from source (with --enable-debug), or rebuild your distro's
package with debug symbols enabled.
> My additions/observations are in blue (html):
>
> volatile UINT32 xxx = 0;
> AcpiTimerLibConstructor (VOID) {
> // Check to see if the PIIX4 Power Management Base Address is already
> enabled
> if ((PciRead8 (PMREGMISC) & PMIOSE) == 0) {
>
> // PMREGMISC = 0xb080, PciRead8 returns 0 so the following is executed
The registers we're talking about here are in different namespaces. See
the PIIX4 spec.
(i)
#define PIIX4_POWER_MANAGEMENT_BUS 0x00
#define PIIX4_POWER_MANAGEMENT_DEVICE 0x01
#define PIIX4_POWER_MANAGEMENT_FUNCTION 0x03
Also from your other mail (from the pci device tree dumped from qemu):
Bus 0, device 1, function 3:
Bridge: PCI device 8086:7113
IRQ 0.
id ""
This is the "PIIX4 Power Management function" (see chapter 7.0 and
section 7.1.2.)
(ii)
#define PIIX4_PCI_POWER_MANAGEMENT_REGISTER(Register) \
PCI_LIB_ADDRESS ( \
PIIX4_POWER_MANAGEMENT_BUS, \
PIIX4_POWER_MANAGEMENT_DEVICE, \
PIIX4_POWER_MANAGEMENT_FUNCTION, \
Register \
)
PCI_LIB_ADDRESS() is an edk2-specific macro that packs the bus, device,
function and PCI config space register arguments into an integer
[MdePkg/Include/Library/PciLib.h]. The packed format is just a shorthand
for the PciLib functions.
(iii)
#define PMREGMISC PIIX4_PCI_POWER_MANAGEMENT_REGISTER (0x80)
So PMREGMISC is just PCI config space register 0x80 (see section
7.1.26). It has nothing to do with the value 0xb000. The lowest bit of
PMREGMISC's contents is called PMIOSE.
(iv)
#define PMBA PIIX4_PCI_POWER_MANAGEMENT_REGISTER (0x40)
Another PCI config space register, this time 0x40. (See section 7.1.10.)
The lowest bit of its contents is always set (we call it PMBA_RTE).
(v)
#define ACPI_TIMER_OFFSET 0x8
This refers to an IO-space register, but it's not an absoulte value,
just an offset from the base set in PMBA. The register is called PMTMR
(section 7.2.4).
In C notation, the connections between the above are, ignoring masks and
constant bits:
- programming the base (AcpiTimerLibConstructor):
if (conf_space[0x80] == 0) {
static const uint16_t PcdAcpiPmBaseAddress = 0xb000;
conf_space[0x40] = PcdAcpiPmBaseAddress;
conf_space[0x80] = 1;
}
- reading the timer (InternalAcpiGetTimerTick):
timer_value = io_space[conf_space[0x40] + 0x8];
Hence delay loops should always read ioport 0xb008.
>
> // If the PIIX4 Power Management Base Address is not programmed,
> // then program the PIIX4 Power Management Base Address from a PCD.
> PciAndThenOr32 (PMBA, (UINT32)(~0x0000FFC0), PcdGet16
> (PcdAcpiPmBaseAddress));
>
> // PcdAcpiPmBaseAddress = 0xb040
No, see above.
>
> // Enable PMBA I/O port decodes in PMREGMISC
> PciOr8 (PMREGMISC, PMIOSE);
> }
> xxx = PciRead32(PMBA); // xxx = 0xb001
That's the correct value. We programmed base 0xb000 and the lowest bit
(PMBA_RTE) always reads as 1.
Laszlo
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