Il 29/09/2014 09:22, Gerd Hoffmann ha scritto: > >> > The one thing I'm a bit unsure about is PciInitializationQ35 >> > (BdsPlatform.c); >> > In PciInitializationPIIX (which used to be plain PciInitialization before >> > this patch), there's a whole bunch of other devices (ide, video, network, >> > etc.) being initialized by writing to registers > That is wrong. The function should only initialize the chipset, i.e > devices 0 (northbridge) and 1 (southbridge). Everything else is just a > shot into the dark, hoping the devices are there. Which is the case in > a default qemu configuration, i.e. if you boot the system with just > "qemu -hda $image" and let qemu add default vga+nic. It is possible to > configure qemu completely different though.
Writes to 0x3d are useless---that is a read-only register. In fact, 0x3d should be _used_ to determine whether to fill in the register at 0x3c, and what value to write. OVMF must write there the GSI number associated to the corresponding INTX pin. See pci_bios_init_device in SeaBIOS's src/fw/pciinit.c. This should be done in a PEI (or is it PI?) driver, not DXE, because it must run on resume from S3. Paolo ------------------------------------------------------------------------------ Slashdot TV. Videos for Nerds. Stuff that Matters. http://pubads.g.doubleclick.net/gampad/clk?id=160591471&iu=/4140/ostg.clktrk _______________________________________________ edk2-devel mailing list edk2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/edk2-devel
